From 8e923f249de02acd6757315f0b6badc28f9c28b7 Mon Sep 17 00:00:00 2001 From: YuhangQ Date: Thu, 9 Mar 2023 13:17:53 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E7=BB=93=E6=9E=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 2 +- exp_result/ATPG-LS_b01.bench.txt | 89 + exp_result/ATPG-LS_b02.bench.txt | 7 + exp_result/ATPG-LS_b03.bench.txt | 125 + exp_result/ATPG-LS_b04.bench.txt | 187 + exp_result/ATPG-LS_b06.bench.txt | 56 + exp_result/ATPG-LS_b07.bench.txt | 301 + exp_result/ATPG-LS_b08.bench.txt | 6134 ++ exp_result/ATPG-LS_b09.bench.txt | 2240 + exp_result/ATPG-LS_b10.bench.txt | 431 + exp_result/ATPG-LS_b11.bench.txt | 1297 + exp_result/ATPG-LS_b12.bench.txt | 10 + exp_result/ATPG-LS_b13.bench.txt | 364 + exp_result/ATPG-LS_b17.bench.txt | 10 + exp_result/ATPG-LS_b20.bench.txt | 10 + exp_result/ATPG-LS_b21.bench.txt | 10 + exp_result/ATPG-LS_b22.bench.txt | 10 + exp_result/ATPG-LS_c1355.bench.txt | 44020 +++++++++++++ exp_result/ATPG-LS_c17.bench.txt | 29 + exp_result/ATPG-LS_c1908.bench.txt | 7669 +++ exp_result/ATPG-LS_c2670.bench.txt | 346 + exp_result/ATPG-LS_c3540.bench.txt | 700 + exp_result/ATPG-LS_c432.bench.txt | 88111 +++++++++++++++++++++++++++ exp_result/ATPG-LS_c499.bench.txt | 19187 ++++++ exp_result/ATPG-LS_c5315.bench.txt | 10 + exp_result/ATPG-LS_c6288.bench.txt | 619 + exp_result/ATPG-LS_c7552.bench.txt | 670 + exp_result/ATPG-LS_c880.bench.txt | 2708 + 28 files changed, 175351 insertions(+), 1 deletion(-) create mode 100644 exp_result/ATPG-LS_b01.bench.txt create mode 100644 exp_result/ATPG-LS_b02.bench.txt create mode 100644 exp_result/ATPG-LS_b03.bench.txt create mode 100644 exp_result/ATPG-LS_b04.bench.txt create mode 100644 exp_result/ATPG-LS_b06.bench.txt create mode 100644 exp_result/ATPG-LS_b07.bench.txt create mode 100644 exp_result/ATPG-LS_b08.bench.txt create mode 100644 exp_result/ATPG-LS_b09.bench.txt create mode 100644 exp_result/ATPG-LS_b10.bench.txt create mode 100644 exp_result/ATPG-LS_b11.bench.txt create mode 100644 exp_result/ATPG-LS_b12.bench.txt create mode 100644 exp_result/ATPG-LS_b13.bench.txt create mode 100644 exp_result/ATPG-LS_b17.bench.txt create mode 100644 exp_result/ATPG-LS_b20.bench.txt create mode 100644 exp_result/ATPG-LS_b21.bench.txt create mode 100644 exp_result/ATPG-LS_b22.bench.txt create mode 100644 exp_result/ATPG-LS_c1355.bench.txt create mode 100644 exp_result/ATPG-LS_c17.bench.txt create mode 100644 exp_result/ATPG-LS_c1908.bench.txt create mode 100644 exp_result/ATPG-LS_c2670.bench.txt create mode 100644 exp_result/ATPG-LS_c3540.bench.txt create mode 100644 exp_result/ATPG-LS_c432.bench.txt create mode 100644 exp_result/ATPG-LS_c499.bench.txt create mode 100644 exp_result/ATPG-LS_c5315.bench.txt create mode 100644 exp_result/ATPG-LS_c6288.bench.txt create mode 100644 exp_result/ATPG-LS_c7552.bench.txt create mode 100644 exp_result/ATPG-LS_c880.bench.txt diff --git a/.gitignore b/.gitignore index 86bc890..311e9bd 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,4 @@ *.o *.d .vscode -*.txt +output.txt diff --git a/exp_result/ATPG-LS_b01.bench.txt b/exp_result/ATPG-LS_b01.bench.txt new file mode 100644 index 0000000..8f82a47 --- /dev/null +++ b/exp_result/ATPG-LS_b01.bench.txt @@ -0,0 +1,89 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b01.bench ... Done. +====== Circuit Statistics ====== +PI: 7 +PO: 7 +Gate: 48 +Stem: 28 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:541. flip_cnt: 0, stem_cnt: 28, fault_cnt:42 +coverage: 43.750% pattern: 1 before: 96 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:145. flip_cnt: 0, stem_cnt: 28, fault_cnt:39 +coverage: 63.542% pattern: 2 before: 54 now: 35 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 68.750% pattern: 3 before: 35 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 +coverage: 76.042% pattern: 4 before: 30 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 78.125% pattern: 5 before: 23 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 78.125% pattern: 5 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 78.125% pattern: 5 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 78.125% pattern: 5 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 78.125% pattern: 5 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:75. flip_cnt: 0, stem_cnt: 28, fault_cnt:32 +coverage: 82.292% pattern: 6 before: 21 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 82.292% pattern: 6 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 82.292% pattern: 6 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 82.292% pattern: 6 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:21 +coverage: 82.292% pattern: 6 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:49. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 +coverage: 86.458% pattern: 7 before: 17 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 28, fault_cnt:34 +coverage: 88.542% pattern: 8 before: 13 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 28, fault_cnt:37 +coverage: 91.667% pattern: 9 before: 11 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 28, fault_cnt:37 +coverage: 94.792% pattern: 10 before: 8 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 28, fault_cnt:31 +coverage: 95.833% pattern: 11 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 28, fault_cnt:31 +coverage: 96.875% pattern: 12 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:31 +coverage: 96.875% pattern: 12 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 +coverage: 97.917% pattern: 13 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 28, fault_cnt:38 +coverage: 97.917% pattern: 13 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 28, fault_cnt:28 +coverage: 98.958% pattern: 14 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 28, fault_cnt:34 +coverage: 100.000% pattern: 15 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 0m0.364s +user 0m0.359s +sys 0m0.004s diff --git a/exp_result/ATPG-LS_b02.bench.txt b/exp_result/ATPG-LS_b02.bench.txt new file mode 100644 index 0000000..4385f16 --- /dev/null +++ b/exp_result/ATPG-LS_b02.bench.txt @@ -0,0 +1,7 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b02.bench ...Error while reading file: DFF is not a valid gate. + +real 0m0.003s +user 0m0.001s +sys 0m0.000s diff --git a/exp_result/ATPG-LS_b03.bench.txt b/exp_result/ATPG-LS_b03.bench.txt new file mode 100644 index 0000000..838fd36 --- /dev/null +++ b/exp_result/ATPG-LS_b03.bench.txt @@ -0,0 +1,125 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b03.bench ... Done. +====== Circuit Statistics ====== +PI: 34 +PO: 34 +Gate: 152 +Stem: 86 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:1483. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 38.487% pattern: 1 before: 304 now: 187 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1222. flip_cnt: 0, stem_cnt: 86, fault_cnt:121 +coverage: 60.526% pattern: 2 before: 187 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:170. flip_cnt: 0, stem_cnt: 86, fault_cnt:107 +coverage: 73.026% pattern: 3 before: 120 now: 82 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 86, fault_cnt:124 +coverage: 79.934% pattern: 4 before: 82 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:62. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 83.224% pattern: 5 before: 61 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:72. flip_cnt: 0, stem_cnt: 86, fault_cnt:113 +coverage: 84.539% pattern: 6 before: 51 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 86, fault_cnt:121 +coverage: 85.526% pattern: 7 before: 47 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 86, fault_cnt:115 +coverage: 89.803% pattern: 8 before: 44 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:138. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 92.434% pattern: 9 before: 31 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:114 +coverage: 93.092% pattern: 10 before: 23 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119 +coverage: 93.092% pattern: 10 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 93.421% pattern: 11 before: 21 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127 +coverage: 93.750% pattern: 12 before: 20 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:122 +coverage: 94.408% pattern: 13 before: 19 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120 +coverage: 94.408% pattern: 13 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:86. flip_cnt: 0, stem_cnt: 86, fault_cnt:111 +coverage: 98.355% pattern: 14 before: 17 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 86, fault_cnt:113 +coverage: 99.013% pattern: 15 before: 5 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 99.342% pattern: 16 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:118 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:119 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:122 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113 +coverage: 99.342% pattern: 16 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:114 +coverage: 99.671% pattern: 17 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:121 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:116 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:117 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:115 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:120 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:109 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:113 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:111 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 86, fault_cnt:124 +coverage: 99.671% pattern: 17 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 86, fault_cnt:127 +coverage: 100.000% pattern: 18 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 0m5.785s +user 0m5.778s +sys 0m0.004s diff --git a/exp_result/ATPG-LS_b04.bench.txt b/exp_result/ATPG-LS_b04.bench.txt new file mode 100644 index 0000000..028dbb2 --- /dev/null +++ b/exp_result/ATPG-LS_b04.bench.txt @@ -0,0 +1,187 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b04.bench ... Done. +====== Circuit Statistics ====== +PI: 77 +PO: 74 +Gate: 587 +Stem: 262 +Level: 7 +================================ +[SOL] flip: 0, stem: 0, fault:3259. flip_cnt: 0, stem_cnt: 262, fault_cnt:298 +coverage: 25.383% pattern: 1 before: 1174 now: 876 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3249. flip_cnt: 0, stem_cnt: 262, fault_cnt:294 +coverage: 39.949% pattern: 2 before: 876 now: 705 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1254. flip_cnt: 0, stem_cnt: 262, fault_cnt:299 +coverage: 45.571% pattern: 3 before: 705 now: 639 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 262, fault_cnt:297 +coverage: 49.915% pattern: 4 before: 639 now: 588 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 262, fault_cnt:304 +coverage: 52.641% pattern: 5 before: 588 now: 556 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 262, fault_cnt:310 +coverage: 53.152% pattern: 6 before: 556 now: 550 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:874. flip_cnt: 0, stem_cnt: 262, fault_cnt:334 +coverage: 57.070% pattern: 7 before: 550 now: 504 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300 +coverage: 57.070% pattern: 7 before: 504 now: 504 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 262, fault_cnt:313 +coverage: 57.325% pattern: 8 before: 504 now: 501 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305 +coverage: 57.325% pattern: 8 before: 501 now: 501 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303 +coverage: 57.325% pattern: 8 before: 501 now: 501 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 262, fault_cnt:301 +coverage: 57.411% pattern: 9 before: 501 now: 500 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 262, fault_cnt:312 +coverage: 58.433% pattern: 10 before: 500 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:307 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:286 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:292 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312 +coverage: 58.433% pattern: 10 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:324 +coverage: 58.603% pattern: 11 before: 488 now: 486 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:317 +coverage: 58.773% pattern: 12 before: 486 now: 484 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:313 +coverage: 58.773% pattern: 12 before: 484 now: 484 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305 +coverage: 58.773% pattern: 12 before: 484 now: 484 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317 +coverage: 58.773% pattern: 12 before: 484 now: 484 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 262, fault_cnt:260 +coverage: 58.944% pattern: 13 before: 484 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:314 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:299 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:318 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:293 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:309 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:333 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:311 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:310 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:320 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:312 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:300 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:322 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:297 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:315 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:304 +coverage: 58.944% pattern: 13 before: 482 now: 482 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2152. flip_cnt: 0, stem_cnt: 262, fault_cnt:376 +coverage: 68.995% pattern: 14 before: 482 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:302 +coverage: 68.995% pattern: 14 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:303 +coverage: 68.995% pattern: 14 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:308 +coverage: 68.995% pattern: 14 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:928. flip_cnt: 0, stem_cnt: 262, fault_cnt:306 +coverage: 73.424% pattern: 15 before: 364 now: 312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:332 +coverage: 73.424% pattern: 15 before: 312 now: 312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:317 +coverage: 73.424% pattern: 15 before: 312 now: 312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:305 +coverage: 73.424% pattern: 15 before: 312 now: 312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:301 +coverage: 73.424% pattern: 15 before: 312 now: 312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 262, fault_cnt:316 +coverage: 73.424% pattern: 15 before: 312 now: 312 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_b06.bench.txt b/exp_result/ATPG-LS_b06.bench.txt new file mode 100644 index 0000000..cf7f372 --- /dev/null +++ b/exp_result/ATPG-LS_b06.bench.txt @@ -0,0 +1,56 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b06.bench ... Done. +====== Circuit Statistics ====== +PI: 11 +PO: 15 +Gate: 56 +Stem: 42 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 42, fault_cnt:44 +coverage: 39.286% pattern: 1 before: 112 now: 68 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:99. flip_cnt: 0, stem_cnt: 42, fault_cnt:44 +coverage: 66.071% pattern: 2 before: 68 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 +coverage: 75.000% pattern: 3 before: 38 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:204. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 +coverage: 86.607% pattern: 4 before: 28 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:56. flip_cnt: 0, stem_cnt: 42, fault_cnt:45 +coverage: 90.179% pattern: 5 before: 15 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 42, fault_cnt:47 +coverage: 91.071% pattern: 6 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 +coverage: 92.857% pattern: 7 before: 10 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 42, fault_cnt:41 +coverage: 93.750% pattern: 8 before: 8 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:9. flip_cnt: 0, stem_cnt: 42, fault_cnt:36 +coverage: 96.429% pattern: 9 before: 7 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 +coverage: 97.321% pattern: 10 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 42, fault_cnt:43 +coverage: 98.214% pattern: 11 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 42, fault_cnt:44 +coverage: 99.107% pattern: 12 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 42, fault_cnt:46 +coverage: 99.107% pattern: 12 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 42, fault_cnt:40 +coverage: 100.000% pattern: 13 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 0m0.098s +user 0m0.093s +sys 0m0.004s diff --git a/exp_result/ATPG-LS_b07.bench.txt b/exp_result/ATPG-LS_b07.bench.txt new file mode 100644 index 0000000..98e8732 --- /dev/null +++ b/exp_result/ATPG-LS_b07.bench.txt @@ -0,0 +1,301 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b07.bench ... Done. +====== Circuit Statistics ====== +PI: 50 +PO: 57 +Gate: 419 +Stem: 224 +Level: 5 +================================ +[SOL] flip: 0, stem: 0, fault:2928. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 29.236% pattern: 1 before: 838 now: 593 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2071. flip_cnt: 0, stem_cnt: 224, fault_cnt:251 +coverage: 42.243% pattern: 2 before: 593 now: 484 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1368. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 50.835% pattern: 3 before: 484 now: 412 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 56.444% pattern: 4 before: 412 now: 365 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 224, fault_cnt:236 +coverage: 57.637% pattern: 5 before: 365 now: 355 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1767. flip_cnt: 0, stem_cnt: 224, fault_cnt:314 +coverage: 68.735% pattern: 6 before: 355 now: 262 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 69.212% pattern: 7 before: 262 now: 258 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:254 +coverage: 70.525% pattern: 8 before: 258 now: 247 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238 +coverage: 70.525% pattern: 8 before: 247 now: 247 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 70.644% pattern: 9 before: 247 now: 246 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:233 +coverage: 70.644% pattern: 9 before: 246 now: 246 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 71.002% pattern: 10 before: 246 now: 243 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249 +coverage: 71.002% pattern: 10 before: 243 now: 243 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:253 +coverage: 71.241% pattern: 11 before: 243 now: 241 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 71.241% pattern: 11 before: 241 now: 241 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247 +coverage: 71.241% pattern: 11 before: 241 now: 241 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 71.838% pattern: 12 before: 241 now: 236 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 224, fault_cnt:217 +coverage: 72.673% pattern: 13 before: 236 now: 229 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 72.673% pattern: 13 before: 229 now: 229 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:242 +coverage: 73.628% pattern: 14 before: 229 now: 221 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 224, fault_cnt:296 +coverage: 79.714% pattern: 15 before: 221 now: 170 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241 +coverage: 79.714% pattern: 15 before: 170 now: 170 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 224, fault_cnt:237 +coverage: 80.072% pattern: 16 before: 170 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 80.072% pattern: 16 before: 167 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241 +coverage: 80.072% pattern: 16 before: 167 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248 +coverage: 80.072% pattern: 16 before: 167 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 80.310% pattern: 17 before: 167 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242 +coverage: 80.310% pattern: 17 before: 165 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 80.310% pattern: 17 before: 165 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 80.310% pattern: 17 before: 165 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 80.310% pattern: 17 before: 165 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235 +coverage: 80.310% pattern: 17 before: 165 now: 165 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:219 +coverage: 80.907% pattern: 18 before: 165 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:232 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:252 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:255 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 80.907% pattern: 18 before: 160 now: 160 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:760. flip_cnt: 0, stem_cnt: 224, fault_cnt:325 +coverage: 85.680% pattern: 19 before: 160 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:242 +coverage: 85.680% pattern: 19 before: 120 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238 +coverage: 85.680% pattern: 19 before: 120 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 85.680% pattern: 19 before: 120 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 85.680% pattern: 19 before: 120 now: 120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:250 +coverage: 85.800% pattern: 20 before: 120 now: 119 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250 +coverage: 85.800% pattern: 20 before: 119 now: 119 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 85.800% pattern: 20 before: 119 now: 119 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 224, fault_cnt:307 +coverage: 87.112% pattern: 21 before: 119 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:218 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:217 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:231 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:228 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 87.112% pattern: 21 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:313 +coverage: 87.709% pattern: 22 before: 108 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 87.709% pattern: 22 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 87.709% pattern: 22 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 87.709% pattern: 22 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235 +coverage: 87.709% pattern: 22 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249 +coverage: 87.709% pattern: 22 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 224, fault_cnt:321 +coverage: 88.783% pattern: 23 before: 103 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:245 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:250 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:234 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:238 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:247 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:241 +coverage: 88.783% pattern: 23 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 224, fault_cnt:322 +coverage: 89.737% pattern: 24 before: 94 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:248 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:236 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:249 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 89.737% pattern: 24 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 224, fault_cnt:244 +coverage: 89.857% pattern: 25 before: 86 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:239 +coverage: 89.857% pattern: 25 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:244 +coverage: 89.857% pattern: 25 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:243 +coverage: 89.857% pattern: 25 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 224, fault_cnt:326 +coverage: 90.453% pattern: 26 before: 85 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:246 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:235 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:254 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:240 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:237 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 224, fault_cnt:324 +coverage: 90.453% pattern: 26 before: 80 now: 80 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_b08.bench.txt b/exp_result/ATPG-LS_b08.bench.txt new file mode 100644 index 0000000..67c865b --- /dev/null +++ b/exp_result/ATPG-LS_b08.bench.txt @@ -0,0 +1,6134 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b08.bench ... Done. +====== Circuit Statistics ====== +PI: 30 +PO: 25 +Gate: 167 +Stem: 98 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:417. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 30.838% pattern: 1 before: 334 now: 231 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:517. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 54.491% pattern: 2 before: 231 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 60.778% pattern: 3 before: 152 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 67.365% pattern: 4 before: 131 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:554. flip_cnt: 0, stem_cnt: 98, fault_cnt:117 +coverage: 76.946% pattern: 5 before: 109 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 79.940% pattern: 6 before: 77 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 79.940% pattern: 6 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 79.940% pattern: 6 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 80.240% pattern: 7 before: 67 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 81.737% pattern: 8 before: 66 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 81.737% pattern: 8 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 81.737% pattern: 8 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 81.737% pattern: 8 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 84.132% pattern: 9 before: 61 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 84.132% pattern: 9 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 85.928% pattern: 10 before: 53 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:43. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 86.826% pattern: 11 before: 47 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 87.126% pattern: 12 before: 44 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:30. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 88.024% pattern: 13 before: 43 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 88.024% pattern: 13 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 88.922% pattern: 14 before: 40 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 88.922% pattern: 14 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 88.922% pattern: 14 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 98, fault_cnt:128 +coverage: 91.317% pattern: 15 before: 37 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 91.317% pattern: 15 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 91.617% pattern: 16 before: 29 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 91.617% pattern: 16 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 91.617% pattern: 16 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 91.916% pattern: 17 before: 28 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 91.916% pattern: 17 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 92.515% pattern: 18 before: 27 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 92.515% pattern: 18 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 94.311% pattern: 19 before: 25 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 94.311% pattern: 19 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 94.611% pattern: 20 before: 19 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 94.611% pattern: 20 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:36. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 95.210% pattern: 21 before: 18 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 95.210% pattern: 21 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 95.509% pattern: 22 before: 16 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 95.509% pattern: 22 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:6. flip_cnt: 0, stem_cnt: 98, fault_cnt:128 +coverage: 95.808% pattern: 23 before: 15 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 96.407% pattern: 24 before: 14 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 96.707% pattern: 25 before: 12 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:133 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 96.707% pattern: 25 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:12. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 97.006% pattern: 26 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 97.006% pattern: 26 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 97.006% pattern: 26 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 97.305% pattern: 27 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:82 +coverage: 97.305% pattern: 27 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 97.605% pattern: 28 before: 9 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 97.605% pattern: 28 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 98, fault_cnt:121 +coverage: 98.204% pattern: 29 before: 8 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.204% pattern: 29 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 98, fault_cnt:126 +coverage: 98.802% pattern: 30 before: 6 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:131 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 98.802% pattern: 30 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:78 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.102% pattern: 31 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:124 +coverage: 99.401% pattern: 32 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:127 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:117 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:82 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:129 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:134 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:80 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:126 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:120 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:117 +coverage: 99.401% pattern: 32 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.701% pattern: 33 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:118 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:120 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:92 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:124 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:97 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:116 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:93 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:95 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:83 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:86 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:109 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:91 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:112 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:115 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:88 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:90 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:98 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:87 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:84 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:114 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:85 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:111 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:104 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:103 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:100 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:107 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:110 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:94 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:102 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:105 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:101 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:99 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:96 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:108 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:89 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 98, fault_cnt:106 +coverage: 99.701% pattern: 33 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 98, fault_cnt:113 +coverage: 100.000% pattern: 34 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 2m38.563s +user 2m38.546s +sys 0m0.004s diff --git a/exp_result/ATPG-LS_b09.bench.txt b/exp_result/ATPG-LS_b09.bench.txt new file mode 100644 index 0000000..2a3cdca --- /dev/null +++ b/exp_result/ATPG-LS_b09.bench.txt @@ -0,0 +1,2240 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b09.bench ... Done. +====== Circuit Statistics ====== +PI: 29 +PO: 29 +Gate: 142 +Stem: 79 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:267. flip_cnt: 0, stem_cnt: 79, fault_cnt:121 +coverage: 42.606% pattern: 1 before: 284 now: 163 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:678. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 72.535% pattern: 2 before: 163 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 79.930% pattern: 3 before: 78 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:195. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 83.803% pattern: 4 before: 57 now: 46 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:45. flip_cnt: 0, stem_cnt: 79, fault_cnt:83 +coverage: 90.493% pattern: 5 before: 46 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 91.549% pattern: 6 before: 27 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 92.958% pattern: 7 before: 24 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 92.958% pattern: 7 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:29. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 95.070% pattern: 8 before: 20 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 95.423% pattern: 9 before: 14 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 95.423% pattern: 9 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:15. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 96.127% pattern: 10 before: 13 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82 +coverage: 96.127% pattern: 10 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 96.127% pattern: 10 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 96.127% pattern: 10 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 96.127% pattern: 10 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 96.127% pattern: 10 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 96.479% pattern: 11 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 96.479% pattern: 11 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 96.831% pattern: 12 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 96.831% pattern: 12 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 9 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.183% pattern: 13 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 97.887% pattern: 14 before: 8 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 97.887% pattern: 14 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 79, fault_cnt:83 +coverage: 98.239% pattern: 15 before: 6 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:78 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.239% pattern: 15 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:10. flip_cnt: 0, stem_cnt: 79, fault_cnt:97 +coverage: 98.592% pattern: 16 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:94 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:99 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:85 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:76 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.592% pattern: 16 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:94 +coverage: 98.944% pattern: 17 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:79 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 98.944% pattern: 17 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:17. flip_cnt: 0, stem_cnt: 79, fault_cnt:94 +coverage: 99.296% pattern: 18 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:101 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:93 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.296% pattern: 18 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 79, fault_cnt:95 +coverage: 99.648% pattern: 19 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:89 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:97 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:87 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:81 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:102 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:92 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:86 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:90 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:103 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:83 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:109 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:120 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:105 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:84 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:112 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:82 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:88 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:117 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:114 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:107 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:115 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:113 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:104 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:110 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:120 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:119 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:106 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:108 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:116 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:118 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 79, fault_cnt:111 +coverage: 99.648% pattern: 19 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 79, fault_cnt:92 +coverage: 100.000% pattern: 20 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 1m21.293s +user 1m21.286s +sys 0m0.000s diff --git a/exp_result/ATPG-LS_b10.bench.txt b/exp_result/ATPG-LS_b10.bench.txt new file mode 100644 index 0000000..5e0327e --- /dev/null +++ b/exp_result/ATPG-LS_b10.bench.txt @@ -0,0 +1,431 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b10.bench ... Done. +====== Circuit Statistics ====== +PI: 28 +PO: 23 +Gate: 182 +Stem: 91 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:1187. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 30.495% pattern: 1 before: 364 now: 253 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 91, fault_cnt:96 +coverage: 41.758% pattern: 2 before: 253 now: 212 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:792. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 53.297% pattern: 3 before: 212 now: 170 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:453. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 67.308% pattern: 4 before: 170 now: 119 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 68.407% pattern: 5 before: 119 now: 115 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 68.956% pattern: 6 before: 115 now: 113 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 74.176% pattern: 7 before: 113 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 76.923% pattern: 8 before: 94 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 77.473% pattern: 9 before: 84 now: 82 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:135. flip_cnt: 0, stem_cnt: 91, fault_cnt:114 +coverage: 79.945% pattern: 10 before: 82 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 79.945% pattern: 10 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 81.044% pattern: 11 before: 73 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 82.692% pattern: 12 before: 69 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 83.242% pattern: 13 before: 63 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:113 +coverage: 84.066% pattern: 14 before: 61 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 84.066% pattern: 14 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 85.440% pattern: 15 before: 58 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 85.440% pattern: 15 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 85.989% pattern: 16 before: 53 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 85.989% pattern: 16 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 85.989% pattern: 16 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 91, fault_cnt:113 +coverage: 89.011% pattern: 17 before: 51 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 89.286% pattern: 18 before: 40 now: 39 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 91, fault_cnt:117 +coverage: 89.560% pattern: 19 before: 39 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98 +coverage: 89.560% pattern: 19 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110 +coverage: 89.560% pattern: 19 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:120 +coverage: 89.560% pattern: 19 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 89.560% pattern: 19 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 90.110% pattern: 20 before: 38 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 90.110% pattern: 20 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 90.110% pattern: 20 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 90.110% pattern: 20 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:118 +coverage: 90.110% pattern: 20 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 91.209% pattern: 21 before: 36 now: 32 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 91.209% pattern: 21 before: 32 now: 32 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 92.033% pattern: 22 before: 32 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 92.033% pattern: 22 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 92.033% pattern: 22 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 92.033% pattern: 22 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 92.033% pattern: 22 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 93.407% pattern: 23 before: 29 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 93.407% pattern: 23 before: 24 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:85 +coverage: 93.407% pattern: 23 before: 24 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113 +coverage: 93.407% pattern: 23 before: 24 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 93.407% pattern: 23 before: 24 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 93.956% pattern: 24 before: 24 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 93.956% pattern: 24 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 94.505% pattern: 25 before: 22 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:7. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 95.604% pattern: 26 before: 20 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 95.604% pattern: 26 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:115 +coverage: 95.879% pattern: 27 before: 16 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:101 +coverage: 95.879% pattern: 27 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 96.429% pattern: 28 before: 15 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:89 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 96.429% pattern: 28 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 96.703% pattern: 29 before: 13 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 96.703% pattern: 29 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110 +coverage: 96.703% pattern: 29 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:59. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 98.077% pattern: 30 before: 12 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 91, fault_cnt:109 +coverage: 98.626% pattern: 31 before: 7 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:115 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:94 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:109 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:98 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:106 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:114 +coverage: 98.626% pattern: 31 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 91, fault_cnt:111 +coverage: 98.901% pattern: 32 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:96 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:113 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:104 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:97 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:95 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:100 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:110 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:93 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:91 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:103 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:107 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:99 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:105 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:102 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 91, fault_cnt:112 +coverage: 98.901% pattern: 32 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:51. flip_cnt: 0, stem_cnt: 91, fault_cnt:108 +coverage: 100.000% pattern: 33 before: 4 now: 0 +checking valid circuit ... result: 1. + +real 0m36.403s +user 0m36.398s +sys 0m0.000s diff --git a/exp_result/ATPG-LS_b11.bench.txt b/exp_result/ATPG-LS_b11.bench.txt new file mode 100644 index 0000000..9bdd5cb --- /dev/null +++ b/exp_result/ATPG-LS_b11.bench.txt @@ -0,0 +1,1297 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b11.bench ... Done. +====== Circuit Statistics ====== +PI: 38 +PO: 37 +Gate: 429 +Stem: 214 +Level: 5 +================================ +[SOL] flip: 0, stem: 0, fault:3640. flip_cnt: 0, stem_cnt: 214, fault_cnt:204 +coverage: 23.776% pattern: 1 before: 858 now: 654 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1805. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 34.848% pattern: 2 before: 654 now: 559 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 39.394% pattern: 3 before: 559 now: 520 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:531. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 42.657% pattern: 4 before: 520 now: 492 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2148. flip_cnt: 0, stem_cnt: 214, fault_cnt:278 +coverage: 55.944% pattern: 5 before: 492 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 57.459% pattern: 6 before: 378 now: 365 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1472. flip_cnt: 0, stem_cnt: 214, fault_cnt:282 +coverage: 66.550% pattern: 7 before: 365 now: 287 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 66.783% pattern: 8 before: 287 now: 285 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 68.065% pattern: 9 before: 285 now: 274 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 214, fault_cnt:153 +coverage: 69.930% pattern: 10 before: 274 now: 258 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 70.396% pattern: 11 before: 258 now: 254 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 70.979% pattern: 12 before: 254 now: 249 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 71.212% pattern: 13 before: 249 now: 247 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 71.212% pattern: 13 before: 247 now: 247 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 71.329% pattern: 14 before: 247 now: 246 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:191 +coverage: 71.445% pattern: 15 before: 246 now: 245 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:159 +coverage: 71.678% pattern: 16 before: 245 now: 243 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:779. flip_cnt: 0, stem_cnt: 214, fault_cnt:279 +coverage: 76.457% pattern: 17 before: 243 now: 202 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202 +coverage: 76.457% pattern: 17 before: 202 now: 202 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 76.457% pattern: 17 before: 202 now: 202 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 76.457% pattern: 17 before: 202 now: 202 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 214, fault_cnt:288 +coverage: 77.622% pattern: 18 before: 202 now: 192 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:150 +coverage: 77.739% pattern: 19 before: 192 now: 191 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:280 +coverage: 78.205% pattern: 20 before: 191 now: 187 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:198 +coverage: 78.322% pattern: 21 before: 187 now: 186 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 78.322% pattern: 21 before: 186 now: 186 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:189 +coverage: 78.555% pattern: 22 before: 186 now: 184 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154 +coverage: 78.555% pattern: 22 before: 184 now: 184 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 78.671% pattern: 23 before: 184 now: 183 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 78.671% pattern: 23 before: 183 now: 183 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 78.671% pattern: 23 before: 183 now: 183 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:722. flip_cnt: 0, stem_cnt: 214, fault_cnt:267 +coverage: 83.100% pattern: 24 before: 183 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 83.100% pattern: 24 before: 145 now: 145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 214, fault_cnt:222 +coverage: 84.382% pattern: 25 before: 145 now: 134 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:188 +coverage: 84.499% pattern: 26 before: 134 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:205 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 84.499% pattern: 26 before: 133 now: 133 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 84.732% pattern: 27 before: 133 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 84.732% pattern: 27 before: 131 now: 131 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 85.664% pattern: 28 before: 131 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 85.664% pattern: 28 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:192 +coverage: 85.781% pattern: 29 before: 123 now: 122 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 214, fault_cnt:276 +coverage: 88.228% pattern: 30 before: 122 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 88.228% pattern: 30 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 88.345% pattern: 31 before: 101 now: 100 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 88.345% pattern: 31 before: 100 now: 100 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 88.345% pattern: 31 before: 100 now: 100 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195 +coverage: 88.345% pattern: 31 before: 100 now: 100 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 88.345% pattern: 31 before: 100 now: 100 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 214, fault_cnt:307 +coverage: 89.744% pattern: 32 before: 100 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 89.744% pattern: 32 before: 88 now: 88 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:203 +coverage: 90.210% pattern: 33 before: 88 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 90.210% pattern: 33 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.210% pattern: 33 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188 +coverage: 90.210% pattern: 33 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 90.210% pattern: 33 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:208 +coverage: 90.676% pattern: 34 before: 84 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:147 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:153 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:188 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 90.676% pattern: 34 before: 80 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:297 +coverage: 90.909% pattern: 35 before: 80 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:204 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 90.909% pattern: 35 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:201 +coverage: 91.259% pattern: 36 before: 78 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:200 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 91.259% pattern: 36 before: 75 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 214, fault_cnt:201 +coverage: 92.191% pattern: 37 before: 75 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:152 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:207 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:199 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 92.191% pattern: 37 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 214, fault_cnt:230 +coverage: 93.240% pattern: 38 before: 67 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:298 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:154 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:196 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:159 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:156 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:186 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.240% pattern: 38 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 214, fault_cnt:296 +coverage: 93.590% pattern: 39 before: 58 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:195 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:155 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:211 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:189 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:194 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:169 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:294 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:293 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:202 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:192 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:185 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:164 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:161 +coverage: 93.590% pattern: 39 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 214, fault_cnt:268 +coverage: 94.755% pattern: 40 before: 55 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 94.755% pattern: 40 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:270 +coverage: 94.872% pattern: 41 before: 45 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:163 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:151 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:168 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:158 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:171 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:165 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 94.872% pattern: 41 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 214, fault_cnt:286 +coverage: 95.338% pattern: 42 before: 44 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:160 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:190 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:191 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:157 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:167 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:268 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:181 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:180 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:172 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:226 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 95.338% pattern: 42 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 214, fault_cnt:294 +coverage: 95.571% pattern: 43 before: 40 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:175 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:193 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:178 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:179 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:183 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:182 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:187 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:177 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:170 +coverage: 95.571% pattern: 43 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 214, fault_cnt:218 +coverage: 95.688% pattern: 44 before: 38 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:198 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:208 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:173 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:166 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:184 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:176 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:174 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 214, fault_cnt:162 +coverage: 95.688% pattern: 44 before: 37 now: 37 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_b12.bench.txt b/exp_result/ATPG-LS_b12.bench.txt new file mode 100644 index 0000000..8b4a6f6 --- /dev/null +++ b/exp_result/ATPG-LS_b12.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b12.bench ... Done. +====== Circuit Statistics ====== +PI: 126 +PO: 127 +Gate: 1039 +Stem: 511 +Level: 5 +================================ diff --git a/exp_result/ATPG-LS_b13.bench.txt b/exp_result/ATPG-LS_b13.bench.txt new file mode 100644 index 0000000..6c352fb --- /dev/null +++ b/exp_result/ATPG-LS_b13.bench.txt @@ -0,0 +1,364 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b13.bench ... Done. +====== Circuit Statistics ====== +PI: 63 +PO: 63 +Gate: 322 +Stem: 187 +Level: 3 +================================ +[SOL] flip: 0, stem: 0, fault:4104. flip_cnt: 0, stem_cnt: 187, fault_cnt:216 +coverage: 33.540% pattern: 1 before: 644 now: 428 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2470. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 53.727% pattern: 2 before: 428 now: 298 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1140. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 63.043% pattern: 3 before: 298 now: 238 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 187, fault_cnt:207 +coverage: 67.702% pattern: 4 before: 238 now: 208 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:211 +coverage: 70.031% pattern: 5 before: 208 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 71.739% pattern: 6 before: 193 now: 182 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 187, fault_cnt:209 +coverage: 72.360% pattern: 7 before: 182 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 187, fault_cnt:233 +coverage: 74.068% pattern: 8 before: 178 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 75.932% pattern: 9 before: 167 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 78.261% pattern: 10 before: 155 now: 140 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 78.571% pattern: 11 before: 140 now: 138 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:213 +coverage: 78.571% pattern: 11 before: 138 now: 138 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 79.814% pattern: 12 before: 138 now: 130 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 80.590% pattern: 13 before: 130 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 187, fault_cnt:226 +coverage: 81.832% pattern: 14 before: 125 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 81.832% pattern: 14 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 81.832% pattern: 14 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 83.385% pattern: 15 before: 117 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 83.385% pattern: 15 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:234 +coverage: 84.317% pattern: 16 before: 107 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 85.093% pattern: 17 before: 101 now: 96 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 85.248% pattern: 18 before: 96 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229 +coverage: 85.248% pattern: 18 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:235 +coverage: 85.248% pattern: 18 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:229 +coverage: 85.714% pattern: 19 before: 95 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216 +coverage: 85.714% pattern: 19 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228 +coverage: 85.714% pattern: 19 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 85.714% pattern: 19 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212 +coverage: 85.714% pattern: 19 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 86.646% pattern: 20 before: 92 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:228 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 86.646% pattern: 20 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 187, fault_cnt:243 +coverage: 90.839% pattern: 21 before: 86 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 90.839% pattern: 21 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226 +coverage: 90.839% pattern: 21 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 90.839% pattern: 21 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 91.770% pattern: 22 before: 59 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:211 +coverage: 91.925% pattern: 23 before: 53 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:231 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:227 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 91.925% pattern: 23 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:25. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 92.702% pattern: 24 before: 52 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 92.702% pattern: 24 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 92.702% pattern: 24 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 92.702% pattern: 24 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 92.702% pattern: 24 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 92.857% pattern: 25 before: 47 now: 46 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:208 +coverage: 92.857% pattern: 25 before: 46 now: 46 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 92.857% pattern: 25 before: 46 now: 46 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 93.012% pattern: 26 before: 46 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 93.012% pattern: 26 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:204 +coverage: 93.168% pattern: 27 before: 45 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 93.323% pattern: 28 before: 44 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 93.789% pattern: 29 before: 43 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 93.789% pattern: 29 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:36. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 94.099% pattern: 30 before: 40 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:230 +coverage: 94.255% pattern: 31 before: 38 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 94.255% pattern: 31 before: 37 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 94.410% pattern: 32 before: 37 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:223 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 94.410% pattern: 32 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 187, fault_cnt:249 +coverage: 95.186% pattern: 33 before: 36 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:218 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:224 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:214 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:204 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:216 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:225 +coverage: 95.186% pattern: 33 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 187, fault_cnt:210 +coverage: 95.342% pattern: 34 before: 31 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:220 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:219 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:230 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:229 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:221 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:215 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:212 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:226 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 187, fault_cnt:217 +coverage: 95.342% pattern: 34 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 187, fault_cnt:222 +coverage: 95.652% pattern: 35 before: 30 now: 28 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_b17.bench.txt b/exp_result/ATPG-LS_b17.bench.txt new file mode 100644 index 0000000..89f92ec --- /dev/null +++ b/exp_result/ATPG-LS_b17.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b17.bench ... Done. +====== Circuit Statistics ====== +PI: 1452 +PO: 1512 +Gate: 23710 +Stem: 8257 +Level: 7 +================================ diff --git a/exp_result/ATPG-LS_b20.bench.txt b/exp_result/ATPG-LS_b20.bench.txt new file mode 100644 index 0000000..786e44c --- /dev/null +++ b/exp_result/ATPG-LS_b20.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b20.bench ... Done. +====== Circuit Statistics ====== +PI: 522 +PO: 512 +Gate: 8734 +Stem: 3428 +Level: 7 +================================ diff --git a/exp_result/ATPG-LS_b21.bench.txt b/exp_result/ATPG-LS_b21.bench.txt new file mode 100644 index 0000000..9906514 --- /dev/null +++ b/exp_result/ATPG-LS_b21.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b21.bench ... Done. +====== Circuit Statistics ====== +PI: 522 +PO: 512 +Gate: 8995 +Stem: 3647 +Level: 8 +================================ diff --git a/exp_result/ATPG-LS_b22.bench.txt b/exp_result/ATPG-LS_b22.bench.txt new file mode 100644 index 0000000..c5c89e5 --- /dev/null +++ b/exp_result/ATPG-LS_b22.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/b22.bench ... Done. +====== Circuit Statistics ====== +PI: 767 +PO: 757 +Gate: 13721 +Stem: 5379 +Level: 8 +================================ diff --git a/exp_result/ATPG-LS_c1355.bench.txt b/exp_result/ATPG-LS_c1355.bench.txt new file mode 100644 index 0000000..7bd0690 --- /dev/null +++ b/exp_result/ATPG-LS_c1355.bench.txt @@ -0,0 +1,44020 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c1355.bench ... Done. +====== Circuit Statistics ====== +PI: 41 +PO: 32 +Gate: 587 +Stem: 299 +Level: 7 +================================ +[SOL] flip: 0, stem: 0, fault:5058. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 30.068% pattern: 1 before: 1174 now: 821 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4128. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 51.363% pattern: 2 before: 821 now: 571 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:333. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 54.344% pattern: 3 before: 571 now: 536 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:280. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 55.622% pattern: 4 before: 536 now: 521 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 60.307% pattern: 5 before: 521 now: 466 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 62.777% pattern: 6 before: 466 now: 437 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:551. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 65.247% pattern: 7 before: 437 now: 408 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 67.632% pattern: 8 before: 408 now: 380 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 72.317% pattern: 9 before: 380 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 72.317% pattern: 9 before: 325 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 72.317% pattern: 9 before: 325 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 72.317% pattern: 9 before: 325 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 72.317% pattern: 9 before: 325 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 72.317% pattern: 9 before: 325 now: 325 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 72.402% pattern: 10 before: 325 now: 324 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 74.446% pattern: 11 before: 324 now: 300 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 75.724% pattern: 12 before: 300 now: 285 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 77.939% pattern: 13 before: 285 now: 259 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 78.279% pattern: 14 before: 259 now: 255 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 78.279% pattern: 14 before: 255 now: 255 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 79.557% pattern: 15 before: 255 now: 240 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 79.557% pattern: 15 before: 240 now: 240 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 81.261% pattern: 16 before: 240 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 81.261% pattern: 16 before: 220 now: 220 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 81.857% pattern: 17 before: 220 now: 213 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 81.942% pattern: 18 before: 213 now: 212 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 82.709% pattern: 19 before: 212 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 83.135% pattern: 20 before: 203 now: 198 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 83.560% pattern: 21 before: 198 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 83.560% pattern: 21 before: 193 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 83.731% pattern: 22 before: 193 now: 191 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 83.816% pattern: 23 before: 191 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 83.816% pattern: 23 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 83.816% pattern: 23 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 83.816% pattern: 23 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 83.816% pattern: 23 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 84.668% pattern: 24 before: 190 now: 180 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 84.838% pattern: 25 before: 180 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 84.838% pattern: 25 before: 178 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 84.838% pattern: 25 before: 178 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 84.838% pattern: 25 before: 178 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 85.264% pattern: 26 before: 178 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 85.264% pattern: 26 before: 173 now: 173 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 85.349% pattern: 27 before: 173 now: 172 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 86.201% pattern: 28 before: 172 now: 162 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.201% pattern: 28 before: 162 now: 162 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 86.201% pattern: 28 before: 162 now: 162 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 86.712% pattern: 29 before: 162 now: 156 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 86.797% pattern: 30 before: 156 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 86.797% pattern: 30 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.797% pattern: 30 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 86.797% pattern: 30 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.797% pattern: 30 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 86.882% pattern: 31 before: 155 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 86.882% pattern: 31 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 87.053% pattern: 32 before: 154 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.053% pattern: 32 before: 152 now: 152 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 87.223% pattern: 33 before: 152 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 87.223% pattern: 33 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.223% pattern: 33 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 87.394% pattern: 34 before: 150 now: 148 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 87.394% pattern: 34 before: 148 now: 148 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 87.394% pattern: 34 before: 148 now: 148 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 87.394% pattern: 34 before: 148 now: 148 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 87.394% pattern: 34 before: 148 now: 148 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 88.160% pattern: 35 before: 148 now: 139 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 88.160% pattern: 35 before: 139 now: 139 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 88.160% pattern: 35 before: 139 now: 139 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 88.160% pattern: 35 before: 139 now: 139 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 88.160% pattern: 35 before: 139 now: 139 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 88.245% pattern: 36 before: 139 now: 138 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 88.245% pattern: 36 before: 138 now: 138 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 88.330% pattern: 37 before: 138 now: 137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 88.330% pattern: 37 before: 137 now: 137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 88.330% pattern: 37 before: 137 now: 137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 88.330% pattern: 37 before: 137 now: 137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 88.330% pattern: 37 before: 137 now: 137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 89.267% pattern: 38 before: 137 now: 126 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 89.267% pattern: 38 before: 126 now: 126 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 89.267% pattern: 38 before: 126 now: 126 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 89.267% pattern: 38 before: 126 now: 126 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 89.353% pattern: 39 before: 126 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 89.353% pattern: 39 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 89.353% pattern: 39 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 89.353% pattern: 39 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 89.523% pattern: 40 before: 125 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 89.523% pattern: 40 before: 123 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 90.375% pattern: 41 before: 123 now: 113 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 90.375% pattern: 41 before: 113 now: 113 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.375% pattern: 41 before: 113 now: 113 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 90.375% pattern: 41 before: 113 now: 113 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 90.460% pattern: 42 before: 113 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 90.460% pattern: 42 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 90.630% pattern: 43 before: 112 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.630% pattern: 43 before: 110 now: 110 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 90.716% pattern: 44 before: 110 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.716% pattern: 44 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.716% pattern: 44 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.716% pattern: 44 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 90.886% pattern: 45 before: 109 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 90.971% pattern: 46 before: 107 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 90.971% pattern: 46 before: 106 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 91.227% pattern: 47 before: 106 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.227% pattern: 47 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.227% pattern: 47 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 91.227% pattern: 47 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.227% pattern: 47 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 91.227% pattern: 47 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 91.397% pattern: 48 before: 103 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 91.397% pattern: 48 before: 101 now: 101 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 91.908% pattern: 49 before: 101 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 91.908% pattern: 49 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 91.908% pattern: 49 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.908% pattern: 49 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.908% pattern: 49 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 91.993% pattern: 50 before: 95 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 91.993% pattern: 50 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 92.164% pattern: 51 before: 94 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 92.164% pattern: 51 before: 92 now: 92 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 92.249% pattern: 52 before: 92 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 92.249% pattern: 52 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 92.675% pattern: 53 before: 91 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 92.675% pattern: 53 before: 86 now: 86 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 92.845% pattern: 54 before: 86 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 92.845% pattern: 54 before: 84 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 93.356% pattern: 55 before: 84 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.356% pattern: 55 before: 78 now: 78 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 93.526% pattern: 56 before: 78 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.526% pattern: 56 before: 76 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 93.697% pattern: 57 before: 76 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 93.697% pattern: 57 before: 74 now: 74 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 94.123% pattern: 58 before: 74 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.123% pattern: 58 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 94.293% pattern: 59 before: 69 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.293% pattern: 59 before: 67 now: 67 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 94.804% pattern: 60 before: 67 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 94.804% pattern: 60 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 94.974% pattern: 61 before: 61 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 95.145% pattern: 62 before: 59 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.145% pattern: 62 before: 57 now: 57 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 95.315% pattern: 63 before: 57 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.315% pattern: 63 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 95.400% pattern: 64 before: 55 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.400% pattern: 64 before: 54 now: 54 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 95.571% pattern: 65 before: 54 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.571% pattern: 65 before: 52 now: 52 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 95.656% pattern: 66 before: 52 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.656% pattern: 66 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 95.826% pattern: 67 before: 51 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.826% pattern: 67 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 95.911% pattern: 68 before: 49 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.911% pattern: 68 before: 48 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.911% pattern: 68 before: 48 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 95.911% pattern: 68 before: 48 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 95.911% pattern: 68 before: 48 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 95.911% pattern: 68 before: 48 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 95.997% pattern: 69 before: 48 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 95.997% pattern: 69 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 96.167% pattern: 70 before: 47 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.167% pattern: 70 before: 45 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 96.252% pattern: 71 before: 45 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.252% pattern: 71 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.252% pattern: 71 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.252% pattern: 71 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.252% pattern: 71 before: 44 now: 44 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 96.337% pattern: 72 before: 44 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 96.337% pattern: 72 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 96.422% pattern: 73 before: 43 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 96.422% pattern: 73 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 96.508% pattern: 74 before: 42 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:344 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.508% pattern: 74 before: 41 now: 41 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 96.593% pattern: 75 before: 41 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.593% pattern: 75 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 96.763% pattern: 76 before: 40 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 96.763% pattern: 76 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 96.934% pattern: 77 before: 38 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 96.934% pattern: 77 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 97.019% pattern: 78 before: 36 now: 35 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.019% pattern: 78 before: 35 now: 35 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 97.189% pattern: 79 before: 35 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.189% pattern: 79 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 97.359% pattern: 80 before: 33 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.359% pattern: 80 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 97.445% pattern: 81 before: 31 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.445% pattern: 81 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 97.615% pattern: 82 before: 30 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.615% pattern: 82 before: 28 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 97.785% pattern: 83 before: 28 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 97.785% pattern: 83 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 97.871% pattern: 84 before: 26 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 97.871% pattern: 84 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.041% pattern: 85 before: 25 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.041% pattern: 85 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.126% pattern: 86 before: 23 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.126% pattern: 86 before: 22 now: 22 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.211% pattern: 87 before: 22 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.211% pattern: 87 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 98.382% pattern: 88 before: 21 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.382% pattern: 88 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.552% pattern: 89 before: 19 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.552% pattern: 89 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.637% pattern: 90 before: 17 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.637% pattern: 90 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 98.722% pattern: 91 before: 16 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.722% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.807% pattern: 92 before: 15 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.807% pattern: 92 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.893% pattern: 93 before: 14 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.893% pattern: 93 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 98.978% pattern: 94 before: 13 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 98.978% pattern: 94 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.063% pattern: 95 before: 12 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:457 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.063% pattern: 95 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.148% pattern: 96 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:433 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.148% pattern: 96 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.233% pattern: 97 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.233% pattern: 97 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.319% pattern: 98 before: 9 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:435 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.319% pattern: 98 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.404% pattern: 99 before: 8 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.404% pattern: 99 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.489% pattern: 100 before: 7 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:454 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.489% pattern: 100 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.574% pattern: 101 before: 6 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:452 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:450 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:346 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.574% pattern: 101 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.659% pattern: 102 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.659% pattern: 102 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:436 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:289 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:438 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:441 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:365 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:367 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:366 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:345 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:276 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:455 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:290 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:453 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:362 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:447 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:449 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:445 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:440 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:287 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:451 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:442 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:443 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:439 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:446 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:448 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:434 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:291 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:444 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:364 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:361 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:351 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:363 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:437 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:349 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:360 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:359 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:352 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:348 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:356 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:278 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:358 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:277 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:357 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:279 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:286 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:192 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:350 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:347 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:280 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:284 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:282 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:288 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:353 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:354 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:355 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:205 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:285 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:283 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:196 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:281 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 299, fault_cnt:200 +coverage: 99.744% pattern: 103 before: 3 now: 3 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c17.bench.txt b/exp_result/ATPG-LS_c17.bench.txt new file mode 100644 index 0000000..db95724 --- /dev/null +++ b/exp_result/ATPG-LS_c17.bench.txt @@ -0,0 +1,29 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c17.bench ... Done. +====== Circuit Statistics ====== +PI: 5 +PO: 2 +Gate: 11 +Stem: 9 +Level: 2 +================================ +[SOL] flip: 0, stem: 0, fault:8. flip_cnt: 0, stem_cnt: 9, fault_cnt:8 +coverage: 36.364% pattern: 1 before: 22 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 9, fault_cnt:9 +coverage: 54.545% pattern: 2 before: 14 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 9, fault_cnt:9 +coverage: 90.909% pattern: 3 before: 10 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 9, fault_cnt:8 +coverage: 90.909% pattern: 3 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2. flip_cnt: 0, stem_cnt: 9, fault_cnt:6 +coverage: 100.000% pattern: 4 before: 2 now: 0 +checking valid circuit ... result: 1. + +real 0m0.004s +user 0m0.002s +sys 0m0.000s diff --git a/exp_result/ATPG-LS_c1908.bench.txt b/exp_result/ATPG-LS_c1908.bench.txt new file mode 100644 index 0000000..fe1d7b0 --- /dev/null +++ b/exp_result/ATPG-LS_c1908.bench.txt @@ -0,0 +1,7669 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c1908.bench ... Done. +====== Circuit Statistics ====== +PI: 33 +PO: 25 +Gate: 913 +Stem: 410 +Level: 12 +================================ +[SOL] flip: 0, stem: 0, fault:9429. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 27.273% pattern: 1 before: 1826 now: 1328 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5572. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 46.440% pattern: 2 before: 1328 now: 978 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2452. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 53.560% pattern: 3 before: 978 now: 848 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 54.819% pattern: 4 before: 848 now: 825 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1235. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 58.379% pattern: 5 before: 825 now: 760 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 58.817% pattern: 6 before: 760 now: 752 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:836. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 61.227% pattern: 7 before: 752 now: 708 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 410, fault_cnt:567 +coverage: 64.239% pattern: 8 before: 708 now: 653 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:343. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 65.279% pattern: 9 before: 653 now: 634 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 65.717% pattern: 10 before: 634 now: 626 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 65.882% pattern: 11 before: 626 now: 623 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 66.101% pattern: 12 before: 623 now: 619 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 66.320% pattern: 13 before: 619 now: 615 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 66.539% pattern: 14 before: 615 now: 611 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 66.594% pattern: 15 before: 611 now: 610 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 66.703% pattern: 16 before: 610 now: 608 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 66.703% pattern: 16 before: 608 now: 608 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 66.813% pattern: 17 before: 608 now: 606 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 66.813% pattern: 17 before: 606 now: 606 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 67.032% pattern: 18 before: 606 now: 602 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 67.032% pattern: 18 before: 602 now: 602 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 67.032% pattern: 18 before: 602 now: 602 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 67.251% pattern: 19 before: 602 now: 598 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 67.251% pattern: 19 before: 598 now: 598 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 67.251% pattern: 19 before: 598 now: 598 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 67.251% pattern: 19 before: 598 now: 598 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2736. flip_cnt: 0, stem_cnt: 410, fault_cnt:640 +coverage: 75.137% pattern: 20 before: 598 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 75.137% pattern: 20 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 75.137% pattern: 20 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 75.137% pattern: 20 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 75.137% pattern: 20 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 75.246% pattern: 21 before: 454 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232 +coverage: 75.246% pattern: 21 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 75.246% pattern: 21 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 75.246% pattern: 21 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 75.246% pattern: 21 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 75.246% pattern: 21 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 75.465% pattern: 22 before: 452 now: 448 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 75.465% pattern: 22 before: 448 now: 448 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 75.520% pattern: 23 before: 448 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 75.520% pattern: 23 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 410, fault_cnt:172 +coverage: 76.616% pattern: 24 before: 447 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 76.616% pattern: 24 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 76.670% pattern: 25 before: 427 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 76.670% pattern: 25 before: 426 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 76.670% pattern: 25 before: 426 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 76.670% pattern: 25 before: 426 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 76.670% pattern: 25 before: 426 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 76.670% pattern: 25 before: 426 now: 426 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 410, fault_cnt:658 +coverage: 79.409% pattern: 26 before: 426 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 79.409% pattern: 26 before: 376 now: 376 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 79.518% pattern: 27 before: 376 now: 374 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 410, fault_cnt:540 +coverage: 80.504% pattern: 28 before: 374 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 80.504% pattern: 28 before: 356 now: 356 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 80.559% pattern: 29 before: 356 now: 355 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 80.559% pattern: 29 before: 355 now: 355 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 80.559% pattern: 29 before: 355 now: 355 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 80.559% pattern: 29 before: 355 now: 355 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:969. flip_cnt: 0, stem_cnt: 410, fault_cnt:628 +coverage: 83.352% pattern: 30 before: 355 now: 304 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 83.352% pattern: 30 before: 304 now: 304 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 83.680% pattern: 31 before: 304 now: 298 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 83.680% pattern: 31 before: 298 now: 298 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 410, fault_cnt:629 +coverage: 84.666% pattern: 32 before: 298 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 84.666% pattern: 32 before: 280 now: 280 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 85.049% pattern: 33 before: 280 now: 273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 85.049% pattern: 33 before: 273 now: 273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 85.049% pattern: 33 before: 273 now: 273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 85.049% pattern: 33 before: 273 now: 273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:557 +coverage: 85.104% pattern: 34 before: 273 now: 272 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 85.104% pattern: 34 before: 272 now: 272 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 85.104% pattern: 34 before: 272 now: 272 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 85.159% pattern: 35 before: 272 now: 271 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 85.159% pattern: 35 before: 271 now: 271 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 85.487% pattern: 36 before: 271 now: 265 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 410, fault_cnt:595 +coverage: 85.761% pattern: 37 before: 265 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 85.761% pattern: 37 before: 260 now: 260 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:538 +coverage: 85.871% pattern: 38 before: 260 now: 258 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 85.871% pattern: 38 before: 258 now: 258 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 410, fault_cnt:651 +coverage: 88.445% pattern: 39 before: 258 now: 211 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:556 +coverage: 88.664% pattern: 40 before: 211 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 88.664% pattern: 40 before: 207 now: 207 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:567 +coverage: 88.883% pattern: 41 before: 207 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 88.883% pattern: 41 before: 203 now: 203 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:582 +coverage: 88.992% pattern: 42 before: 203 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542 +coverage: 88.992% pattern: 42 before: 201 now: 201 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:220 +coverage: 89.430% pattern: 43 before: 201 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 89.430% pattern: 43 before: 193 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 89.430% pattern: 43 before: 193 now: 193 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:568 +coverage: 89.595% pattern: 44 before: 193 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 89.595% pattern: 44 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 89.595% pattern: 44 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 89.595% pattern: 44 before: 190 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:589 +coverage: 89.704% pattern: 45 before: 190 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:227 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 89.704% pattern: 45 before: 188 now: 188 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 410, fault_cnt:623 +coverage: 90.307% pattern: 46 before: 188 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 90.307% pattern: 46 before: 177 now: 177 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 410, fault_cnt:549 +coverage: 91.512% pattern: 47 before: 177 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:566 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 91.512% pattern: 47 before: 155 now: 155 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 91.731% pattern: 48 before: 155 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 91.731% pattern: 48 before: 151 now: 151 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:591 +coverage: 91.785% pattern: 49 before: 151 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:592 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 91.785% pattern: 49 before: 150 now: 150 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:421. flip_cnt: 0, stem_cnt: 410, fault_cnt:585 +coverage: 93.154% pattern: 50 before: 150 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:590 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438 +coverage: 93.154% pattern: 50 before: 125 now: 125 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:585 +coverage: 93.209% pattern: 51 before: 125 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 93.209% pattern: 51 before: 124 now: 124 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:563 +coverage: 93.373% pattern: 52 before: 124 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:621 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 93.373% pattern: 52 before: 121 now: 121 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:617 +coverage: 93.593% pattern: 53 before: 121 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:599 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:249 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 93.593% pattern: 53 before: 117 now: 117 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:596 +coverage: 93.757% pattern: 54 before: 117 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:645 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:206 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:225 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 93.757% pattern: 54 before: 114 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 93.866% pattern: 55 before: 114 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 93.866% pattern: 55 before: 112 now: 112 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 94.031% pattern: 56 before: 112 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 94.031% pattern: 56 before: 109 now: 109 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:176 +coverage: 94.085% pattern: 57 before: 109 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 94.085% pattern: 57 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579 +coverage: 94.085% pattern: 57 before: 108 now: 108 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:633 +coverage: 94.140% pattern: 58 before: 108 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:550 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:645 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:595 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:216 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:646 +coverage: 94.140% pattern: 58 before: 107 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:597 +coverage: 94.359% pattern: 59 before: 107 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:573 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 94.359% pattern: 59 before: 103 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:628 +coverage: 94.578% pattern: 60 before: 103 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:559 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 94.578% pattern: 60 before: 99 now: 99 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:647 +coverage: 94.797% pattern: 61 before: 99 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:584 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:128 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:635 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 94.797% pattern: 61 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:584 +coverage: 95.016% pattern: 62 before: 95 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 95.016% pattern: 62 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 95.016% pattern: 62 before: 91 now: 91 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:537 +coverage: 95.235% pattern: 63 before: 91 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:630 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:608 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 95.235% pattern: 63 before: 87 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:642 +coverage: 95.345% pattern: 64 before: 87 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:600 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:545 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 95.345% pattern: 64 before: 85 now: 85 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 410, fault_cnt:591 +coverage: 95.783% pattern: 65 before: 85 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:165 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:246 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 95.783% pattern: 65 before: 77 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 95.838% pattern: 66 before: 77 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:537 +coverage: 96.057% pattern: 67 before: 76 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:148 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:656 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:546 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 96.057% pattern: 67 before: 72 now: 72 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 410, fault_cnt:548 +coverage: 96.386% pattern: 68 before: 72 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:562 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441 +coverage: 96.386% pattern: 68 before: 66 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 96.440% pattern: 69 before: 66 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:209 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:593 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:567 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:219 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:646 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:437 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:626 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:132 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:599 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.440% pattern: 69 before: 65 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:633 +coverage: 96.659% pattern: 70 before: 65 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:628 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:597 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.659% pattern: 70 before: 61 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:272 +coverage: 96.824% pattern: 71 before: 61 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:204 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:551 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:539 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:225 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:620 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 96.824% pattern: 71 before: 58 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 96.933% pattern: 72 before: 58 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 96.933% pattern: 72 before: 56 now: 56 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:580 +coverage: 96.988% pattern: 73 before: 56 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 96.988% pattern: 73 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:587 +coverage: 96.988% pattern: 73 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 96.988% pattern: 73 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 96.988% pattern: 73 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 96.988% pattern: 73 before: 55 now: 55 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.097% pattern: 74 before: 55 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:536 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.097% pattern: 74 before: 53 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 53 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:627 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:433 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:650 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:251 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:176 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:544 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:217 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:651 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:220 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.207% pattern: 75 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 97.317% pattern: 76 before: 51 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:555 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:588 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:602 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 97.317% pattern: 76 before: 49 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:624 +coverage: 97.426% pattern: 77 before: 49 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.426% pattern: 77 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:164 +coverage: 97.426% pattern: 77 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.426% pattern: 77 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 97.426% pattern: 77 before: 47 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:638 +coverage: 97.645% pattern: 78 before: 47 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:624 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.645% pattern: 78 before: 43 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:534 +coverage: 97.700% pattern: 79 before: 43 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:211 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:560 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:575 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:575 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:212 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.700% pattern: 79 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:271 +coverage: 97.809% pattern: 80 before: 42 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:538 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:556 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:553 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:179 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:658 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:559 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:576 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:567 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.809% pattern: 80 before: 40 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:646 +coverage: 97.919% pattern: 81 before: 40 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:444 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:551 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:582 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:215 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:181 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:569 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:537 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:553 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:552 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:535 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:162 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:586 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:458 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:439 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:223 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:563 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:201 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:483 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:441 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 97.919% pattern: 81 before: 38 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:644 +coverage: 98.028% pattern: 82 before: 38 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:601 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:198 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:640 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:583 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:543 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:594 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:587 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:245 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:455 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:541 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:456 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:565 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:481 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:197 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:463 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:166 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:629 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:530 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:142 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:431 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:442 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:210 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:479 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:547 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:243 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:133 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.028% pattern: 82 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:222 +coverage: 98.138% pattern: 83 before: 36 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.138% pattern: 83 before: 34 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 410, fault_cnt:631 +coverage: 98.193% pattern: 84 before: 34 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:641 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:476 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:203 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:202 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.193% pattern: 84 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:573 +coverage: 98.302% pattern: 85 before: 33 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:568 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:461 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.302% pattern: 85 before: 31 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:645 +coverage: 98.412% pattern: 86 before: 31 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:636 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:180 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:478 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:565 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:485 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:632 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:490 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:250 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:464 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:638 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:450 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:164 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:585 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.412% pattern: 86 before: 29 now: 29 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:541 +coverage: 98.576% pattern: 87 before: 29 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:213 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:449 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:247 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:580 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:459 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:529 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:462 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:223 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:634 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:471 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:589 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:231 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:438 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 98.576% pattern: 87 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 410, fault_cnt:270 +coverage: 98.740% pattern: 88 before: 26 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:474 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:492 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:554 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:141 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:453 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:550 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:577 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:443 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:578 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:518 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:186 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:480 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:460 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:454 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:533 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:560 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:134 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:232 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.740% pattern: 88 before: 23 now: 23 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:563 +coverage: 98.850% pattern: 89 before: 23 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:649 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:523 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:440 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:622 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:137 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:593 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:446 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:542 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:187 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:139 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:234 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:484 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:630 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:143 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:482 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:527 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:626 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:196 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 98.850% pattern: 89 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 410, fault_cnt:622 +coverage: 99.069% pattern: 90 before: 21 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:451 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:150 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:526 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:470 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:639 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:230 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:513 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:472 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:136 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:517 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:610 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:609 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:448 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:512 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:493 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:199 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:652 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:183 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:193 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:241 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:556 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:558 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:522 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:494 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:496 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:242 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:233 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:574 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:525 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:138 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:244 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:222 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:521 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:491 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:473 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:546 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:184 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:504 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:140 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:195 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:468 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:640 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:528 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:447 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:457 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:465 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:452 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:531 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:466 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:218 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:469 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:467 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:237 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:475 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:135 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:564 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:509 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:581 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:516 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:511 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:514 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:507 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:144 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:488 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:477 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:506 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:240 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:549 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:497 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:191 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:500 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:236 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:557 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:508 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:445 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:189 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:495 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:501 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:515 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:532 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:239 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:502 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:194 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:235 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:571 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:498 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:182 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:145 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:505 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 99.069% pattern: 90 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 410, fault_cnt:640 +coverage: 99.179% pattern: 91 before: 17 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:190 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:519 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:591 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:486 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:520 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:524 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:238 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:192 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:200 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:487 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:221 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:579 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:510 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:499 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:503 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:489 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:185 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 410, fault_cnt:188 +coverage: 99.179% pattern: 91 before: 15 now: 15 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c2670.bench.txt b/exp_result/ATPG-LS_c2670.bench.txt new file mode 100644 index 0000000..f66d219 --- /dev/null +++ b/exp_result/ATPG-LS_c2670.bench.txt @@ -0,0 +1,346 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c2670.bench ... Done. +====== Circuit Statistics ====== +PI: 233 +PO: 140 +Gate: 1426 +Stem: 696 +Level: 12 +================================ +[SOL] flip: 0, stem: 0, fault:13379. flip_cnt: 0, stem_cnt: 696, fault_cnt:707 +coverage: 24.790% pattern: 1 before: 2852 now: 2145 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5187. flip_cnt: 0, stem_cnt: 696, fault_cnt:536 +coverage: 34.362% pattern: 2 before: 2145 now: 1872 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:6579. flip_cnt: 0, stem_cnt: 696, fault_cnt:707 +coverage: 49.649% pattern: 3 before: 1872 now: 1436 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2783. flip_cnt: 0, stem_cnt: 696, fault_cnt:723 +coverage: 55.049% pattern: 4 before: 1436 now: 1282 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 696, fault_cnt:739 +coverage: 57.854% pattern: 5 before: 1282 now: 1202 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2871. flip_cnt: 0, stem_cnt: 696, fault_cnt:635 +coverage: 63.359% pattern: 6 before: 1202 now: 1045 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 696, fault_cnt:487 +coverage: 64.341% pattern: 7 before: 1045 now: 1017 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1444. flip_cnt: 0, stem_cnt: 696, fault_cnt:678 +coverage: 67.006% pattern: 8 before: 1017 now: 941 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:663 +coverage: 67.882% pattern: 9 before: 941 now: 916 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 696, fault_cnt:639 +coverage: 69.776% pattern: 10 before: 916 now: 862 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:544 +coverage: 70.161% pattern: 11 before: 862 now: 851 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:545 +coverage: 70.757% pattern: 12 before: 851 now: 834 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:523. flip_cnt: 0, stem_cnt: 696, fault_cnt:626 +coverage: 71.844% pattern: 13 before: 834 now: 803 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:274. flip_cnt: 0, stem_cnt: 696, fault_cnt:513 +coverage: 72.721% pattern: 14 before: 803 now: 778 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 696, fault_cnt:626 +coverage: 73.107% pattern: 15 before: 778 now: 767 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 696, fault_cnt:615 +coverage: 73.633% pattern: 16 before: 767 now: 752 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:513 +coverage: 74.053% pattern: 17 before: 752 now: 740 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 696, fault_cnt:733 +coverage: 74.509% pattern: 18 before: 740 now: 727 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:244. flip_cnt: 0, stem_cnt: 696, fault_cnt:462 +coverage: 75.070% pattern: 19 before: 727 now: 711 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:563 +coverage: 75.386% pattern: 20 before: 711 now: 702 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574 +coverage: 75.386% pattern: 20 before: 702 now: 702 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:619 +coverage: 75.456% pattern: 21 before: 702 now: 700 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:562 +coverage: 75.596% pattern: 22 before: 700 now: 696 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4. flip_cnt: 0, stem_cnt: 696, fault_cnt:534 +coverage: 75.631% pattern: 23 before: 696 now: 695 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:439 +coverage: 75.631% pattern: 23 before: 695 now: 695 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:569 +coverage: 75.842% pattern: 24 before: 695 now: 689 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:694 +coverage: 75.982% pattern: 25 before: 689 now: 685 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 696, fault_cnt:573 +coverage: 76.297% pattern: 26 before: 685 now: 676 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 696, fault_cnt:602 +coverage: 76.928% pattern: 27 before: 676 now: 658 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479 +coverage: 76.928% pattern: 27 before: 658 now: 658 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:41. flip_cnt: 0, stem_cnt: 696, fault_cnt:604 +coverage: 77.034% pattern: 28 before: 658 now: 655 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 696, fault_cnt:567 +coverage: 77.174% pattern: 29 before: 655 now: 651 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:534 +coverage: 77.174% pattern: 29 before: 651 now: 651 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:646 +coverage: 77.174% pattern: 29 before: 651 now: 651 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:571 +coverage: 77.244% pattern: 30 before: 651 now: 649 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:497 +coverage: 77.244% pattern: 30 before: 649 now: 649 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 696, fault_cnt:540 +coverage: 77.840% pattern: 31 before: 649 now: 632 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594 +coverage: 77.840% pattern: 31 before: 632 now: 632 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:479 +coverage: 77.840% pattern: 31 before: 632 now: 632 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:557 +coverage: 77.910% pattern: 32 before: 632 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:490 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:442 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:494 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:630 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:476 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:573 +coverage: 77.910% pattern: 32 before: 630 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 696, fault_cnt:688 +coverage: 78.647% pattern: 33 before: 630 now: 609 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:624 +coverage: 78.647% pattern: 33 before: 609 now: 609 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:539 +coverage: 78.647% pattern: 33 before: 609 now: 609 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:438 +coverage: 78.647% pattern: 33 before: 609 now: 609 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:588 +coverage: 78.857% pattern: 34 before: 609 now: 603 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:521 +coverage: 78.892% pattern: 35 before: 603 now: 602 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:599 +coverage: 78.962% pattern: 36 before: 602 now: 600 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 696, fault_cnt:655 +coverage: 79.839% pattern: 37 before: 600 now: 575 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:609 +coverage: 79.839% pattern: 37 before: 575 now: 575 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:583 +coverage: 79.874% pattern: 38 before: 575 now: 574 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 696, fault_cnt:756 +coverage: 80.435% pattern: 39 before: 574 now: 558 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:516 +coverage: 80.435% pattern: 39 before: 558 now: 558 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:771 +coverage: 80.505% pattern: 40 before: 558 now: 556 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:609 +coverage: 80.540% pattern: 41 before: 556 now: 555 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:523 +coverage: 80.540% pattern: 41 before: 555 now: 555 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:655 +coverage: 80.540% pattern: 41 before: 555 now: 555 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:629 +coverage: 80.540% pattern: 41 before: 555 now: 555 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 696, fault_cnt:671 +coverage: 80.610% pattern: 42 before: 555 now: 553 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:555 +coverage: 80.891% pattern: 43 before: 553 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:667 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:583 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:588 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:689 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:665 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:444 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:453 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:482 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:470 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:559 +coverage: 80.891% pattern: 43 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 696, fault_cnt:609 +coverage: 81.171% pattern: 44 before: 545 now: 537 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:611 +coverage: 81.206% pattern: 45 before: 537 now: 536 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:581 +coverage: 81.241% pattern: 46 before: 536 now: 535 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:681 +coverage: 81.241% pattern: 46 before: 535 now: 535 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:520 +coverage: 81.452% pattern: 47 before: 535 now: 529 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:698 +coverage: 81.452% pattern: 47 before: 529 now: 529 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:594 +coverage: 81.452% pattern: 47 before: 529 now: 529 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:613 +coverage: 81.487% pattern: 48 before: 529 now: 528 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:530 +coverage: 81.487% pattern: 48 before: 528 now: 528 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:499 +coverage: 81.487% pattern: 48 before: 528 now: 528 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:541 +coverage: 81.697% pattern: 49 before: 528 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:641 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:436 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:678 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:596 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:574 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:568 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:715 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:531 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:592 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:643 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:735 +coverage: 81.697% pattern: 49 before: 522 now: 522 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 696, fault_cnt:643 +coverage: 81.942% pattern: 50 before: 522 now: 515 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 696, fault_cnt:705 +coverage: 82.153% pattern: 51 before: 515 now: 509 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:598 +coverage: 82.153% pattern: 51 before: 509 now: 509 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:468 +coverage: 82.153% pattern: 51 before: 509 now: 509 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 696, fault_cnt:513 +coverage: 82.188% pattern: 52 before: 509 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:554 +coverage: 82.188% pattern: 52 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:509 +coverage: 82.188% pattern: 52 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:553 +coverage: 82.188% pattern: 52 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:590 +coverage: 82.188% pattern: 52 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:501 +coverage: 82.188% pattern: 52 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 696, fault_cnt:560 +coverage: 82.609% pattern: 53 before: 508 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 696, fault_cnt:693 +coverage: 82.609% pattern: 53 before: 496 now: 496 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c3540.bench.txt b/exp_result/ATPG-LS_c3540.bench.txt new file mode 100644 index 0000000..8a35090 --- /dev/null +++ b/exp_result/ATPG-LS_c3540.bench.txt @@ -0,0 +1,700 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c3540.bench ... Done. +====== Circuit Statistics ====== +PI: 50 +PO: 22 +Gate: 1719 +Stem: 605 +Level: 14 +================================ +[SOL] flip: 0, stem: 0, fault:11041. flip_cnt: 0, stem_cnt: 605, fault_cnt:582 +coverage: 16.928% pattern: 1 before: 3438 now: 2856 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:7292. flip_cnt: 0, stem_cnt: 605, fault_cnt:477 +coverage: 28.272% pattern: 2 before: 2856 now: 2466 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4577. flip_cnt: 0, stem_cnt: 605, fault_cnt:456 +coverage: 35.340% pattern: 3 before: 2466 now: 2223 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3730. flip_cnt: 0, stem_cnt: 605, fault_cnt:535 +coverage: 41.245% pattern: 4 before: 2223 now: 2020 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2679. flip_cnt: 0, stem_cnt: 605, fault_cnt:453 +coverage: 45.346% pattern: 5 before: 2020 now: 1879 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5093. flip_cnt: 0, stem_cnt: 605, fault_cnt:658 +coverage: 53.170% pattern: 6 before: 1879 now: 1610 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 605, fault_cnt:305 +coverage: 54.741% pattern: 7 before: 1610 now: 1556 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:273 +coverage: 55.381% pattern: 8 before: 1556 now: 1534 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 605, fault_cnt:396 +coverage: 56.923% pattern: 9 before: 1534 now: 1481 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1672. flip_cnt: 0, stem_cnt: 605, fault_cnt:464 +coverage: 59.482% pattern: 10 before: 1481 now: 1393 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:328 +coverage: 59.948% pattern: 11 before: 1393 now: 1377 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 605, fault_cnt:364 +coverage: 61.547% pattern: 12 before: 1377 now: 1322 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:931. flip_cnt: 0, stem_cnt: 605, fault_cnt:435 +coverage: 62.973% pattern: 13 before: 1322 now: 1273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 605, fault_cnt:506 +coverage: 63.642% pattern: 14 before: 1273 now: 1250 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:304 +coverage: 64.107% pattern: 15 before: 1250 now: 1234 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1843. flip_cnt: 0, stem_cnt: 605, fault_cnt:631 +coverage: 66.928% pattern: 16 before: 1234 now: 1137 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:479 +coverage: 67.423% pattern: 17 before: 1137 now: 1120 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:301 +coverage: 67.685% pattern: 18 before: 1120 now: 1111 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:893. flip_cnt: 0, stem_cnt: 605, fault_cnt:475 +coverage: 69.052% pattern: 19 before: 1111 now: 1064 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:316 +coverage: 69.168% pattern: 20 before: 1064 now: 1060 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:570. flip_cnt: 0, stem_cnt: 605, fault_cnt:424 +coverage: 70.041% pattern: 21 before: 1060 now: 1030 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:494. flip_cnt: 0, stem_cnt: 605, fault_cnt:507 +coverage: 70.797% pattern: 22 before: 1030 now: 1004 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:457 +coverage: 71.844% pattern: 23 before: 1004 now: 968 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:421 +coverage: 72.368% pattern: 24 before: 968 now: 950 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1216. flip_cnt: 0, stem_cnt: 605, fault_cnt:488 +coverage: 74.229% pattern: 25 before: 950 now: 886 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:684. flip_cnt: 0, stem_cnt: 605, fault_cnt:537 +coverage: 75.276% pattern: 26 before: 886 now: 850 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:608. flip_cnt: 0, stem_cnt: 605, fault_cnt:571 +coverage: 76.207% pattern: 27 before: 850 now: 818 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:513. flip_cnt: 0, stem_cnt: 605, fault_cnt:573 +coverage: 76.992% pattern: 28 before: 818 now: 791 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 605, fault_cnt:642 +coverage: 77.487% pattern: 29 before: 791 now: 774 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:632 +coverage: 77.778% pattern: 30 before: 774 now: 764 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 605, fault_cnt:401 +coverage: 78.418% pattern: 31 before: 764 now: 742 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:445 +coverage: 78.505% pattern: 32 before: 742 now: 739 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:567 +coverage: 78.592% pattern: 33 before: 739 now: 736 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:216 +coverage: 78.738% pattern: 34 before: 736 now: 731 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:513 +coverage: 78.738% pattern: 34 before: 731 now: 731 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572 +coverage: 78.738% pattern: 34 before: 731 now: 731 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:366 +coverage: 78.738% pattern: 34 before: 731 now: 731 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:480 +coverage: 79.145% pattern: 35 before: 731 now: 717 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:423 +coverage: 79.727% pattern: 36 before: 717 now: 697 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:458 +coverage: 80.076% pattern: 37 before: 697 now: 685 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:341 +coverage: 80.163% pattern: 38 before: 685 now: 682 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 605, fault_cnt:506 +coverage: 80.337% pattern: 39 before: 682 now: 676 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:523 +coverage: 80.890% pattern: 40 before: 676 now: 657 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:361. flip_cnt: 0, stem_cnt: 605, fault_cnt:479 +coverage: 81.443% pattern: 41 before: 657 now: 638 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:469 +coverage: 81.472% pattern: 42 before: 638 now: 637 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:643 +coverage: 81.617% pattern: 43 before: 637 now: 632 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:557 +coverage: 81.617% pattern: 43 before: 632 now: 632 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:455 +coverage: 81.763% pattern: 44 before: 632 now: 627 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:517 +coverage: 81.850% pattern: 45 before: 627 now: 624 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:520 +coverage: 82.083% pattern: 46 before: 624 now: 616 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:396 +coverage: 82.083% pattern: 46 before: 616 now: 616 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:539 +coverage: 82.112% pattern: 47 before: 616 now: 615 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:344 +coverage: 82.315% pattern: 48 before: 615 now: 608 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:478 +coverage: 82.461% pattern: 49 before: 608 now: 603 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:613 +coverage: 82.752% pattern: 50 before: 603 now: 593 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:468 +coverage: 82.752% pattern: 50 before: 593 now: 593 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:454 +coverage: 82.839% pattern: 51 before: 593 now: 590 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:328 +coverage: 82.839% pattern: 51 before: 590 now: 590 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451 +coverage: 82.839% pattern: 51 before: 590 now: 590 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:402 +coverage: 82.868% pattern: 52 before: 590 now: 589 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369 +coverage: 82.868% pattern: 52 before: 589 now: 589 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:434 +coverage: 82.868% pattern: 52 before: 589 now: 589 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:539 +coverage: 82.926% pattern: 53 before: 589 now: 587 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:489 +coverage: 82.926% pattern: 53 before: 587 now: 587 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:465 +coverage: 82.926% pattern: 53 before: 587 now: 587 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:367 +coverage: 82.955% pattern: 54 before: 587 now: 586 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:371 +coverage: 83.072% pattern: 55 before: 586 now: 582 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 605, fault_cnt:616 +coverage: 83.537% pattern: 56 before: 582 now: 566 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:366 +coverage: 83.566% pattern: 57 before: 566 now: 565 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:241 +coverage: 83.566% pattern: 57 before: 565 now: 565 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:454 +coverage: 83.595% pattern: 58 before: 565 now: 564 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:394 +coverage: 83.595% pattern: 58 before: 564 now: 564 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:469 +coverage: 83.595% pattern: 58 before: 564 now: 564 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 605, fault_cnt:442 +coverage: 84.002% pattern: 59 before: 564 now: 550 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510 +coverage: 84.002% pattern: 59 before: 550 now: 550 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447 +coverage: 84.002% pattern: 59 before: 550 now: 550 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:503 +coverage: 84.264% pattern: 60 before: 550 now: 541 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:191 +coverage: 84.264% pattern: 60 before: 541 now: 541 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:337 +coverage: 84.264% pattern: 60 before: 541 now: 541 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 605, fault_cnt:413 +coverage: 85.079% pattern: 61 before: 541 now: 513 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:569 +coverage: 85.195% pattern: 62 before: 513 now: 509 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:529 +coverage: 85.224% pattern: 63 before: 509 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293 +coverage: 85.224% pattern: 63 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:306 +coverage: 85.224% pattern: 63 before: 508 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:516 +coverage: 85.282% pattern: 64 before: 508 now: 506 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:290 +coverage: 85.311% pattern: 65 before: 506 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451 +coverage: 85.311% pattern: 65 before: 505 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532 +coverage: 85.311% pattern: 65 before: 505 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:309 +coverage: 85.311% pattern: 65 before: 505 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:480 +coverage: 85.311% pattern: 65 before: 505 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:333 +coverage: 85.340% pattern: 66 before: 505 now: 504 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 605, fault_cnt:507 +coverage: 85.573% pattern: 67 before: 504 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423 +coverage: 85.573% pattern: 67 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:429 +coverage: 85.573% pattern: 67 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483 +coverage: 85.573% pattern: 67 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:551 +coverage: 85.718% pattern: 68 before: 496 now: 491 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:425 +coverage: 85.748% pattern: 69 before: 491 now: 490 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285 +coverage: 85.748% pattern: 69 before: 490 now: 490 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:385 +coverage: 86.009% pattern: 70 before: 490 now: 481 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:415 +coverage: 86.009% pattern: 70 before: 481 now: 481 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:288 +coverage: 86.009% pattern: 70 before: 481 now: 481 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:490 +coverage: 86.097% pattern: 71 before: 481 now: 478 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 605, fault_cnt:396 +coverage: 86.678% pattern: 72 before: 478 now: 458 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:467 +coverage: 86.678% pattern: 72 before: 458 now: 458 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:451 +coverage: 86.969% pattern: 73 before: 458 now: 448 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:387 +coverage: 86.969% pattern: 73 before: 448 now: 448 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:127 +coverage: 86.969% pattern: 73 before: 448 now: 448 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:453 +coverage: 86.998% pattern: 74 before: 448 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:591 +coverage: 86.998% pattern: 74 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:481 +coverage: 86.998% pattern: 74 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:544 +coverage: 86.998% pattern: 74 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:450 +coverage: 86.998% pattern: 74 before: 447 now: 447 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:307 +coverage: 87.260% pattern: 75 before: 447 now: 438 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:508 +coverage: 87.289% pattern: 76 before: 438 now: 437 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:572 +coverage: 87.289% pattern: 76 before: 437 now: 437 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:404 +coverage: 87.289% pattern: 76 before: 437 now: 437 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:565 +coverage: 87.289% pattern: 76 before: 437 now: 437 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:387 +coverage: 87.405% pattern: 77 before: 437 now: 433 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:604 +coverage: 87.405% pattern: 77 before: 433 now: 433 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:567 +coverage: 87.405% pattern: 77 before: 433 now: 433 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:602 +coverage: 87.522% pattern: 78 before: 433 now: 429 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522 +coverage: 87.522% pattern: 78 before: 429 now: 429 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:400 +coverage: 87.522% pattern: 78 before: 429 now: 429 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:537 +coverage: 87.522% pattern: 78 before: 429 now: 429 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:551 +coverage: 87.522% pattern: 78 before: 429 now: 429 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:383 +coverage: 87.580% pattern: 79 before: 429 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:336 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:512 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:432 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:475 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:257 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:239 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:526 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495 +coverage: 87.580% pattern: 79 before: 427 now: 427 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:520 +coverage: 87.638% pattern: 80 before: 427 now: 425 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 605, fault_cnt:529 +coverage: 87.842% pattern: 81 before: 425 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:318 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:370 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:334 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:228 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:510 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:292 +coverage: 87.842% pattern: 81 before: 418 now: 418 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 605, fault_cnt:586 +coverage: 88.191% pattern: 82 before: 418 now: 406 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:341 +coverage: 88.191% pattern: 82 before: 406 now: 406 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:315 +coverage: 88.191% pattern: 82 before: 406 now: 406 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:451 +coverage: 88.191% pattern: 82 before: 406 now: 406 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 605, fault_cnt:393 +coverage: 88.336% pattern: 83 before: 406 now: 401 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:483 +coverage: 88.336% pattern: 83 before: 401 now: 401 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:602 +coverage: 88.598% pattern: 84 before: 401 now: 392 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:308 +coverage: 88.598% pattern: 84 before: 392 now: 392 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:552 +coverage: 88.598% pattern: 84 before: 392 now: 392 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:427 +coverage: 88.598% pattern: 84 before: 392 now: 392 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:392 +coverage: 88.627% pattern: 85 before: 392 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:436 +coverage: 88.627% pattern: 85 before: 391 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:576 +coverage: 88.627% pattern: 85 before: 391 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:523 +coverage: 88.627% pattern: 85 before: 391 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:518 +coverage: 88.627% pattern: 85 before: 391 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:558 +coverage: 88.627% pattern: 85 before: 391 now: 391 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:459 +coverage: 88.656% pattern: 86 before: 391 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:401 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:369 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:253 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:530 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:559 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:236 +coverage: 88.656% pattern: 86 before: 390 now: 390 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:634 +coverage: 88.714% pattern: 87 before: 390 now: 388 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:478 +coverage: 88.714% pattern: 87 before: 388 now: 388 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269 +coverage: 88.714% pattern: 87 before: 388 now: 388 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 605, fault_cnt:519 +coverage: 89.005% pattern: 88 before: 388 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:484 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:447 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:461 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:504 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:488 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:314 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:285 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:473 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:626 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:495 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:600 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:520 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:595 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:464 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:460 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:272 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:459 +coverage: 89.005% pattern: 88 before: 378 now: 378 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 605, fault_cnt:416 +coverage: 89.529% pattern: 89 before: 378 now: 360 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:578 +coverage: 89.587% pattern: 90 before: 360 now: 358 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:423 +coverage: 89.616% pattern: 91 before: 358 now: 357 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:443 +coverage: 89.616% pattern: 91 before: 357 now: 357 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377 +coverage: 89.616% pattern: 91 before: 357 now: 357 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 605, fault_cnt:342 +coverage: 89.732% pattern: 92 before: 357 now: 353 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:249 +coverage: 89.732% pattern: 92 before: 353 now: 353 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:343 +coverage: 89.732% pattern: 92 before: 353 now: 353 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:508 +coverage: 89.732% pattern: 92 before: 353 now: 353 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 605, fault_cnt:486 +coverage: 89.791% pattern: 93 before: 353 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:477 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:359 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:279 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:502 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:539 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:562 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:452 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:516 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:463 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:423 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:532 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:269 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:499 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:474 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:360 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:283 +coverage: 89.791% pattern: 93 before: 351 now: 351 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 605, fault_cnt:313 +coverage: 89.820% pattern: 94 before: 351 now: 350 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:507 +coverage: 89.820% pattern: 94 before: 350 now: 350 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 605, fault_cnt:430 +coverage: 90.081% pattern: 95 before: 350 now: 341 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:374 +coverage: 90.081% pattern: 95 before: 341 now: 341 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:487 +coverage: 90.081% pattern: 95 before: 341 now: 341 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:522 +coverage: 90.081% pattern: 95 before: 341 now: 341 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 605, fault_cnt:395 +coverage: 90.169% pattern: 96 before: 341 now: 338 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:377 +coverage: 90.169% pattern: 96 before: 338 now: 338 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:293 +coverage: 90.169% pattern: 96 before: 338 now: 338 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 605, fault_cnt:545 +coverage: 90.169% pattern: 96 before: 338 now: 338 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c432.bench.txt b/exp_result/ATPG-LS_c432.bench.txt new file mode 100644 index 0000000..1078c90 --- /dev/null +++ b/exp_result/ATPG-LS_c432.bench.txt @@ -0,0 +1,88111 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c432.bench ... Done. +====== Circuit Statistics ====== +PI: 36 +PO: 7 +Gate: 196 +Stem: 96 +Level: 6 +================================ +[SOL] flip: 0, stem: 0, fault:422. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 12.245% pattern: 1 before: 392 now: 344 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:158. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 24.235% pattern: 2 before: 344 now: 297 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:753. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 34.439% pattern: 3 before: 297 now: 257 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 39.541% pattern: 4 before: 257 now: 237 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 40.051% pattern: 5 before: 237 now: 235 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:439. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 46.684% pattern: 6 before: 235 now: 209 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1045. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 60.714% pattern: 7 before: 209 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 60.714% pattern: 7 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 60.714% pattern: 7 before: 154 now: 154 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:334. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 65.816% pattern: 8 before: 154 now: 134 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:532. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 72.959% pattern: 9 before: 134 now: 106 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 75.765% pattern: 10 before: 106 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:223. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 79.592% pattern: 11 before: 95 now: 80 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 82.398% pattern: 12 before: 80 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 84.949% pattern: 13 before: 69 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 86.480% pattern: 14 before: 59 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 87.500% pattern: 15 before: 53 now: 49 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 88.520% pattern: 16 before: 49 now: 45 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:140. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 90.561% pattern: 17 before: 45 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 91.327% pattern: 18 before: 37 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 91.327% pattern: 18 before: 34 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 91.837% pattern: 19 before: 34 now: 32 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 93.112% pattern: 20 before: 32 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 93.112% pattern: 20 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 93.112% pattern: 20 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 93.367% pattern: 21 before: 27 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 95.663% pattern: 22 before: 26 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 95.663% pattern: 22 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 95.918% pattern: 23 before: 17 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 95.918% pattern: 23 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 95.918% pattern: 23 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 97.449% pattern: 24 before: 16 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 97.449% pattern: 24 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 97.704% pattern: 25 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 97.959% pattern: 26 before: 9 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 98.724% pattern: 27 before: 8 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 98.724% pattern: 27 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 98.724% pattern: 27 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 98.724% pattern: 27 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 98.724% pattern: 27 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 98.724% pattern: 27 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 98.980% pattern: 28 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 98.980% pattern: 28 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:127 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:125 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:110 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:112 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:122 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:124 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:121 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:111 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:109 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:86 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:22 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:99 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:103 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:120 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:108 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:28 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:96 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:29 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:26 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:101 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:30 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:93 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:113 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:94 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:64 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:123 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:58 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:102 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:81 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:105 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:67 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:33 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:32 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:106 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:73 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:85 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:74 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:114 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:83 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:35 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:44 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:97 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:90 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:53 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:69 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:95 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:24 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:70 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:89 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:78 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:98 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:87 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:76 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:71 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:21 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:104 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:77 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:68 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:100 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:115 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:48 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:61 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:36 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:63 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:47 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:116 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:117 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:40 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:66 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:51 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:84 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:45 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:54 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:55 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:41 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:57 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:52 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:59 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:38 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:91 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:88 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:118 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:60 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:92 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:25 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:50 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:82 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:72 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:43 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:79 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:27 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:34 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:56 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:37 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:62 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:49 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:75 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:39 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:119 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:65 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:107 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:42 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:80 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:46 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 96, fault_cnt:31 +coverage: 99.235% pattern: 29 before: 3 now: 3 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c499.bench.txt b/exp_result/ATPG-LS_c499.bench.txt new file mode 100644 index 0000000..0a79198 --- /dev/null +++ b/exp_result/ATPG-LS_c499.bench.txt @@ -0,0 +1,19187 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c499.bench ... Done. +====== Circuit Statistics ====== +PI: 41 +PO: 32 +Gate: 243 +Stem: 99 +Level: 5 +================================ +[SOL] flip: 0, stem: 0, fault:1330. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 34.774% pattern: 1 before: 486 now: 317 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:576. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 43.827% pattern: 2 before: 317 now: 273 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 47.119% pattern: 3 before: 273 now: 257 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 47.942% pattern: 4 before: 257 now: 253 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:817. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 56.790% pattern: 5 before: 253 now: 210 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 56.790% pattern: 5 before: 210 now: 210 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 60.905% pattern: 6 before: 210 now: 190 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 63.374% pattern: 7 before: 190 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 63.374% pattern: 7 before: 178 now: 178 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:48. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 70.576% pattern: 8 before: 178 now: 143 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 72.840% pattern: 9 before: 143 now: 132 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 72.840% pattern: 9 before: 132 now: 132 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:163. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 74.691% pattern: 10 before: 132 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:342. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 78.395% pattern: 11 before: 123 now: 105 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 78.807% pattern: 12 before: 105 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 80.453% pattern: 13 before: 103 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 80.453% pattern: 13 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 80.453% pattern: 13 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 80.453% pattern: 13 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.453% pattern: 13 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.453% pattern: 13 before: 95 now: 95 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 80.658% pattern: 14 before: 95 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 80.658% pattern: 14 before: 94 now: 94 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:34. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 81.687% pattern: 15 before: 94 now: 89 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 81.687% pattern: 15 before: 89 now: 89 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 82.099% pattern: 16 before: 89 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 82.922% pattern: 17 before: 87 now: 83 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 82.922% pattern: 17 before: 83 now: 83 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 82.922% pattern: 17 before: 83 now: 83 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 82.922% pattern: 17 before: 83 now: 83 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 82.922% pattern: 17 before: 83 now: 83 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 83.333% pattern: 18 before: 83 now: 81 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 83.333% pattern: 18 before: 81 now: 81 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 83.745% pattern: 19 before: 81 now: 79 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 83.745% pattern: 19 before: 79 now: 79 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 83.745% pattern: 19 before: 79 now: 79 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 83.745% pattern: 19 before: 79 now: 79 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 84.156% pattern: 20 before: 79 now: 77 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 84.568% pattern: 21 before: 77 now: 75 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 84.979% pattern: 22 before: 75 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 84.979% pattern: 22 before: 73 now: 73 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 85.391% pattern: 23 before: 73 now: 71 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 85.391% pattern: 23 before: 71 now: 71 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 85.391% pattern: 23 before: 71 now: 71 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 85.391% pattern: 23 before: 71 now: 71 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 85.802% pattern: 24 before: 71 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 85.802% pattern: 24 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 85.802% pattern: 24 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 85.802% pattern: 24 before: 69 now: 69 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 86.626% pattern: 25 before: 69 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 87.037% pattern: 26 before: 65 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 87.037% pattern: 26 before: 63 now: 63 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 87.860% pattern: 27 before: 63 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 87.860% pattern: 27 before: 59 now: 59 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 88.066% pattern: 28 before: 59 now: 58 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 89.712% pattern: 29 before: 58 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 89.712% pattern: 29 before: 50 now: 50 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:151. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 91.358% pattern: 30 before: 50 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 91.358% pattern: 30 before: 42 now: 42 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 93.004% pattern: 31 before: 42 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 93.004% pattern: 31 before: 34 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 93.827% pattern: 32 before: 34 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 93.827% pattern: 32 before: 30 now: 30 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 94.650% pattern: 33 before: 30 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 94.650% pattern: 33 before: 26 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 95.679% pattern: 34 before: 26 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.679% pattern: 34 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 95.679% pattern: 34 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 95.885% pattern: 35 before: 21 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 95.885% pattern: 35 before: 20 now: 20 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.091% pattern: 36 before: 20 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.091% pattern: 36 before: 19 now: 19 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:18. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 96.296% pattern: 37 before: 19 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.296% pattern: 37 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 18 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.502% pattern: 38 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.708% pattern: 39 before: 17 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.708% pattern: 39 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 96.914% pattern: 40 before: 16 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 96.914% pattern: 40 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.119% pattern: 41 before: 15 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 97.119% pattern: 41 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.325% pattern: 42 before: 14 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.325% pattern: 42 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 97.531% pattern: 43 before: 13 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.531% pattern: 43 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.531% pattern: 43 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.531% pattern: 43 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.531% pattern: 43 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.531% pattern: 43 before: 12 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.737% pattern: 44 before: 12 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.737% pattern: 44 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.942% pattern: 45 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 97.942% pattern: 45 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.148% pattern: 46 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.148% pattern: 46 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.354% pattern: 47 before: 9 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 98.354% pattern: 47 before: 8 now: 8 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.560% pattern: 48 before: 8 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.560% pattern: 48 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:16. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.765% pattern: 49 before: 7 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 98.765% pattern: 49 before: 6 now: 6 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.971% pattern: 50 before: 6 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 98.971% pattern: 50 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.177% pattern: 51 before: 5 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.177% pattern: 51 before: 4 now: 4 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 4 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.383% pattern: 52 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:11. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.588% pattern: 53 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:168 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:156 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:199 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:160 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:164 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:138 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:139 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:140 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:96 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:165 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:133 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:192 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:134 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:132 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:137 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:109 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:169 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:135 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:157 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:161 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:100 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 99, fault_cnt:104 +coverage: 99.794% pattern: 54 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5. flip_cnt: 0, stem_cnt: 99, fault_cnt:200 +coverage: 100.000% pattern: 55 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 9m9.017s +user 9m8.925s +sys 0m0.056s diff --git a/exp_result/ATPG-LS_c5315.bench.txt b/exp_result/ATPG-LS_c5315.bench.txt new file mode 100644 index 0000000..a4f6bb3 --- /dev/null +++ b/exp_result/ATPG-LS_c5315.bench.txt @@ -0,0 +1,10 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c5315.bench ... Done. +====== Circuit Statistics ====== +PI: 178 +PO: 123 +Gate: 2485 +Stem: 984 +Level: 10 +================================ diff --git a/exp_result/ATPG-LS_c6288.bench.txt b/exp_result/ATPG-LS_c6288.bench.txt new file mode 100644 index 0000000..c7aa804 --- /dev/null +++ b/exp_result/ATPG-LS_c6288.bench.txt @@ -0,0 +1,619 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c6288.bench ... Done. +====== Circuit Statistics ====== +PI: 32 +PO: 32 +Gate: 2448 +Stem: 1488 +Level: 7 +================================ +[SOL] flip: 0, stem: 0, fault:41910. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2217 +coverage: 45.282% pattern: 1 before: 4896 now: 2679 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:21592. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 68.566% pattern: 2 before: 2679 now: 1539 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:11922. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206 +coverage: 81.536% pattern: 3 before: 1539 now: 904 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5196. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 87.132% pattern: 4 before: 904 now: 630 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4078. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 91.585% pattern: 5 before: 630 now: 412 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1786. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 93.505% pattern: 6 before: 412 now: 318 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177 +coverage: 94.771% pattern: 7 before: 318 now: 256 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:798. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 95.629% pattern: 8 before: 256 now: 214 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:646. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 96.324% pattern: 9 before: 214 now: 180 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1026. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2145 +coverage: 97.426% pattern: 10 before: 180 now: 126 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 97.896% pattern: 11 before: 126 now: 103 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206 +coverage: 98.019% pattern: 12 before: 103 now: 97 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:190. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 98.223% pattern: 13 before: 97 now: 87 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:209. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 98.448% pattern: 14 before: 87 now: 76 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194 +coverage: 98.754% pattern: 15 before: 76 now: 61 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180 +coverage: 99.020% pattern: 16 before: 61 now: 48 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174 +coverage: 99.183% pattern: 17 before: 48 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194 +coverage: 99.244% pattern: 18 before: 40 now: 37 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 99.306% pattern: 19 before: 37 now: 34 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.367% pattern: 20 before: 34 now: 31 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2168 +coverage: 99.449% pattern: 21 before: 31 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.469% pattern: 22 before: 27 now: 26 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.489% pattern: 23 before: 26 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2160 +coverage: 99.510% pattern: 24 before: 25 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 99.510% pattern: 24 before: 24 now: 24 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186 +coverage: 99.571% pattern: 25 before: 24 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.571% pattern: 25 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.571% pattern: 25 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.571% pattern: 25 before: 21 now: 21 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.632% pattern: 26 before: 21 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 99.632% pattern: 26 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202 +coverage: 99.632% pattern: 26 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199 +coverage: 99.653% pattern: 27 before: 18 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2158 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2166 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2169 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2211 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2206 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2175 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2221 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2157 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2170 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2209 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2229 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2215 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2203 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2180 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2161 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2173 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2179 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2162 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2181 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2186 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2185 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2171 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2167 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2193 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2163 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2197 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2202 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2164 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2190 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2174 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2216 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2198 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2176 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2204 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2201 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2205 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2191 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2178 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2212 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2189 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2188 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2200 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2195 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2184 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2196 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2182 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2210 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2194 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2183 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2192 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2177 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2187 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2165 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1488, fault_cnt:2199 +coverage: 99.653% pattern: 27 before: 17 now: 17 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c7552.bench.txt b/exp_result/ATPG-LS_c7552.bench.txt new file mode 100644 index 0000000..037778d --- /dev/null +++ b/exp_result/ATPG-LS_c7552.bench.txt @@ -0,0 +1,670 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c7552.bench ... Done. +====== Circuit Statistics ====== +PI: 207 +PO: 108 +Gate: 3719 +Stem: 1537 +Level: 10 +================================ +[SOL] flip: 0, stem: 0, fault:31574. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1667 +coverage: 22.412% pattern: 1 before: 7438 now: 5771 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:23913. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1701 +coverage: 40.656% pattern: 2 before: 5771 now: 4414 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:13051. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593 +coverage: 50.094% pattern: 3 before: 4414 now: 3712 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:5949. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 +coverage: 54.329% pattern: 4 before: 3712 now: 3397 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:6654. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 +coverage: 59.196% pattern: 5 before: 3397 now: 3035 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4089. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1580 +coverage: 62.140% pattern: 6 before: 3035 now: 2816 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3109. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1443 +coverage: 64.372% pattern: 7 before: 2816 now: 2650 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:6042. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1750 +coverage: 68.647% pattern: 8 before: 2650 now: 2332 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:4459. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1716 +coverage: 71.847% pattern: 9 before: 2332 now: 2094 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1653. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 +coverage: 73.017% pattern: 10 before: 2094 now: 2007 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1121. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1430 +coverage: 73.810% pattern: 11 before: 2007 now: 1948 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:7467. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2099 +coverage: 79.094% pattern: 12 before: 1948 now: 1555 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1522 +coverage: 79.766% pattern: 13 before: 1555 now: 1505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:950. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1594 +coverage: 80.438% pattern: 14 before: 1505 now: 1455 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1676. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1648 +coverage: 81.675% pattern: 15 before: 1455 now: 1363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:951. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 +coverage: 82.361% pattern: 16 before: 1363 now: 1312 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1634. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681 +coverage: 83.517% pattern: 17 before: 1312 now: 1226 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1450 +coverage: 84.041% pattern: 18 before: 1226 now: 1187 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1442 +coverage: 84.136% pattern: 19 before: 1187 now: 1180 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453 +coverage: 84.364% pattern: 20 before: 1180 now: 1163 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:855. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1559 +coverage: 84.969% pattern: 21 before: 1163 now: 1118 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1178. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1681 +coverage: 85.803% pattern: 22 before: 1118 now: 1056 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1426 +coverage: 85.803% pattern: 22 before: 1056 now: 1056 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1007. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1759 +coverage: 86.515% pattern: 23 before: 1056 now: 1003 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1412 +coverage: 86.636% pattern: 24 before: 1003 now: 994 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487 +coverage: 86.650% pattern: 25 before: 994 now: 993 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:437. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1565 +coverage: 86.959% pattern: 26 before: 993 now: 970 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 +coverage: 86.986% pattern: 27 before: 970 now: 968 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1410 +coverage: 87.161% pattern: 28 before: 968 now: 955 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:589. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582 +coverage: 87.577% pattern: 29 before: 955 now: 924 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482 +coverage: 87.591% pattern: 30 before: 924 now: 923 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1508 +coverage: 87.927% pattern: 31 before: 923 now: 898 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1509 +coverage: 87.981% pattern: 32 before: 898 now: 894 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1609 +coverage: 88.196% pattern: 33 before: 894 now: 878 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 +coverage: 88.518% pattern: 34 before: 878 now: 854 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1064. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1930 +coverage: 89.271% pattern: 35 before: 854 now: 798 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1542 +coverage: 89.567% pattern: 36 before: 798 now: 776 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:380. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1546 +coverage: 89.836% pattern: 37 before: 776 now: 756 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:285. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1877 +coverage: 90.038% pattern: 38 before: 756 now: 741 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1523 +coverage: 90.266% pattern: 39 before: 741 now: 724 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1468 +coverage: 90.266% pattern: 39 before: 724 now: 724 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:456. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836 +coverage: 90.589% pattern: 40 before: 724 now: 700 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 +coverage: 90.643% pattern: 41 before: 700 now: 696 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:399. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1632 +coverage: 90.925% pattern: 42 before: 696 now: 675 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:741. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1829 +coverage: 91.449% pattern: 43 before: 675 now: 636 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1530 +coverage: 91.517% pattern: 44 before: 636 now: 631 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1653 +coverage: 91.543% pattern: 45 before: 631 now: 629 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1950 +coverage: 91.772% pattern: 46 before: 629 now: 612 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 +coverage: 91.812% pattern: 47 before: 612 now: 609 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534 +coverage: 91.853% pattern: 48 before: 609 now: 606 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537 +coverage: 91.960% pattern: 49 before: 606 now: 598 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579 +coverage: 91.974% pattern: 50 before: 598 now: 597 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551 +coverage: 91.974% pattern: 50 before: 597 now: 597 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645 +coverage: 92.001% pattern: 51 before: 597 now: 595 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465 +coverage: 92.001% pattern: 51 before: 595 now: 595 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1585 +coverage: 92.108% pattern: 52 before: 595 now: 587 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1862 +coverage: 92.135% pattern: 53 before: 587 now: 585 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1505 +coverage: 92.202% pattern: 54 before: 585 now: 580 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:114. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486 +coverage: 92.283% pattern: 55 before: 580 now: 574 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1435 +coverage: 92.283% pattern: 55 before: 574 now: 574 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1423 +coverage: 92.350% pattern: 56 before: 574 now: 569 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1763 +coverage: 92.404% pattern: 57 before: 569 now: 565 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 +coverage: 92.511% pattern: 58 before: 565 now: 557 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1436 +coverage: 92.511% pattern: 58 before: 557 now: 557 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419 +coverage: 92.511% pattern: 58 before: 557 now: 557 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1666 +coverage: 92.525% pattern: 59 before: 557 now: 556 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1564 +coverage: 92.552% pattern: 60 before: 556 now: 554 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1516 +coverage: 92.606% pattern: 61 before: 554 now: 550 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1655 +coverage: 92.673% pattern: 62 before: 550 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607 +coverage: 92.673% pattern: 62 before: 545 now: 545 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:475. flip_cnt: 0, stem_cnt: 1537, fault_cnt:2158 +coverage: 93.009% pattern: 63 before: 545 now: 520 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1497 +coverage: 93.036% pattern: 64 before: 520 now: 518 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658 +coverage: 93.076% pattern: 65 before: 518 now: 515 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1833 +coverage: 93.076% pattern: 65 before: 515 now: 515 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470 +coverage: 93.076% pattern: 65 before: 515 now: 515 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1603 +coverage: 93.170% pattern: 66 before: 515 now: 508 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1562 +coverage: 93.197% pattern: 67 before: 508 now: 506 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1866 +coverage: 93.197% pattern: 67 before: 506 now: 506 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1837 +coverage: 93.211% pattern: 68 before: 506 now: 505 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1634 +coverage: 93.278% pattern: 69 before: 505 now: 500 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1725 +coverage: 93.318% pattern: 70 before: 500 now: 497 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1582 +coverage: 93.332% pattern: 71 before: 497 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1477 +coverage: 93.332% pattern: 71 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1427 +coverage: 93.332% pattern: 71 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1645 +coverage: 93.332% pattern: 71 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1462 +coverage: 93.332% pattern: 71 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1796 +coverage: 93.332% pattern: 71 before: 496 now: 496 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1657 +coverage: 93.439% pattern: 72 before: 496 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1526 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1571 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1449 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1583 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499 +coverage: 93.439% pattern: 72 before: 488 now: 488 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1690 +coverage: 93.560% pattern: 73 before: 488 now: 479 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1587 +coverage: 93.614% pattern: 74 before: 479 now: 475 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543 +coverage: 93.614% pattern: 74 before: 475 now: 475 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1457 +coverage: 93.614% pattern: 74 before: 475 now: 475 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513 +coverage: 93.654% pattern: 75 before: 475 now: 472 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1425 +coverage: 93.654% pattern: 75 before: 472 now: 472 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876 +coverage: 93.708% pattern: 76 before: 472 now: 468 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1778 +coverage: 93.708% pattern: 76 before: 468 now: 468 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1431 +coverage: 93.721% pattern: 77 before: 468 now: 467 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 +coverage: 93.775% pattern: 78 before: 467 now: 463 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1481 +coverage: 93.802% pattern: 79 before: 463 now: 461 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592 +coverage: 93.802% pattern: 79 before: 461 now: 461 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1804 +coverage: 93.802% pattern: 79 before: 461 now: 461 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1605 +coverage: 93.816% pattern: 80 before: 461 now: 460 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1668 +coverage: 93.842% pattern: 81 before: 460 now: 458 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1840 +coverage: 93.842% pattern: 81 before: 458 now: 458 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441 +coverage: 93.842% pattern: 81 before: 458 now: 458 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1662 +coverage: 93.869% pattern: 82 before: 458 now: 456 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452 +coverage: 93.869% pattern: 82 before: 456 now: 456 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1448 +coverage: 93.869% pattern: 82 before: 456 now: 456 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1592 +coverage: 93.869% pattern: 82 before: 456 now: 456 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 +coverage: 93.869% pattern: 82 before: 456 now: 456 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1575 +coverage: 93.896% pattern: 83 before: 456 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555 +coverage: 93.896% pattern: 83 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1503 +coverage: 93.896% pattern: 83 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606 +coverage: 93.896% pattern: 83 before: 454 now: 454 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 +coverage: 93.923% pattern: 84 before: 454 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572 +coverage: 93.923% pattern: 84 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1506 +coverage: 93.923% pattern: 84 before: 452 now: 452 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:323. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1544 +coverage: 94.152% pattern: 85 before: 452 now: 435 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1441 +coverage: 94.152% pattern: 85 before: 435 now: 435 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1487 +coverage: 94.152% pattern: 85 before: 435 now: 435 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1572 +coverage: 94.152% pattern: 85 before: 435 now: 435 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:304. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1944 +coverage: 94.367% pattern: 86 before: 435 now: 419 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1555 +coverage: 94.367% pattern: 86 before: 419 now: 419 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1453 +coverage: 94.367% pattern: 86 before: 419 now: 419 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1828 +coverage: 94.367% pattern: 86 before: 419 now: 419 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1570 +coverage: 94.407% pattern: 87 before: 419 now: 416 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1760 +coverage: 94.434% pattern: 88 before: 416 now: 414 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478 +coverage: 94.434% pattern: 88 before: 414 now: 414 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1486 +coverage: 94.434% pattern: 88 before: 414 now: 414 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1478 +coverage: 94.474% pattern: 89 before: 414 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1469 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1621 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1658 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1428 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1568 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 +coverage: 94.474% pattern: 89 before: 411 now: 411 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1593 +coverage: 94.568% pattern: 90 before: 411 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1520 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1638 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1458 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1534 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1876 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1561 +coverage: 94.568% pattern: 90 before: 404 now: 404 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1502 +coverage: 94.595% pattern: 91 before: 404 now: 402 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1616 +coverage: 94.595% pattern: 91 before: 402 now: 402 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 +coverage: 94.622% pattern: 92 before: 402 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1868 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1746 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1537 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1514 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1484 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1627 +coverage: 94.622% pattern: 92 before: 400 now: 400 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1566 +coverage: 94.649% pattern: 93 before: 400 now: 398 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1472 +coverage: 94.649% pattern: 93 before: 398 now: 398 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1931 +coverage: 94.824% pattern: 94 before: 398 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1464 +coverage: 94.824% pattern: 94 before: 385 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1535 +coverage: 94.824% pattern: 94 before: 385 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1591 +coverage: 94.824% pattern: 94 before: 385 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1606 +coverage: 94.824% pattern: 94 before: 385 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1452 +coverage: 94.824% pattern: 94 before: 385 now: 385 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1820 +coverage: 94.851% pattern: 95 before: 385 now: 383 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1717 +coverage: 94.864% pattern: 96 before: 383 now: 382 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1742 +coverage: 94.878% pattern: 97 before: 382 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1474 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1513 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1577 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1897 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1576 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1483 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1607 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1473 +coverage: 94.878% pattern: 97 before: 381 now: 381 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1543 +coverage: 94.905% pattern: 98 before: 381 now: 379 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1482 +coverage: 94.905% pattern: 98 before: 379 now: 379 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1465 +coverage: 94.905% pattern: 98 before: 379 now: 379 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:228. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1910 +coverage: 95.066% pattern: 99 before: 379 now: 367 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1437 +coverage: 95.066% pattern: 99 before: 367 now: 367 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1698 +coverage: 95.066% pattern: 99 before: 367 now: 367 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1495 +coverage: 95.079% pattern: 100 before: 367 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1419 +coverage: 95.079% pattern: 100 before: 366 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1550 +coverage: 95.079% pattern: 100 before: 366 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1826 +coverage: 95.079% pattern: 100 before: 366 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1712 +coverage: 95.079% pattern: 100 before: 366 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573 +coverage: 95.079% pattern: 100 before: 366 now: 366 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1492 +coverage: 95.106% pattern: 101 before: 366 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1869 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1499 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1529 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1510 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1578 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1878 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1470 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1563 +coverage: 95.106% pattern: 101 before: 364 now: 364 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1637 +coverage: 95.120% pattern: 102 before: 364 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1444 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1494 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1551 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1945 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1623 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1684 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1539 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1519 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1463 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1579 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1573 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1409 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1512 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1836 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1556 +coverage: 95.120% pattern: 102 before: 363 now: 363 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1646 +coverage: 95.133% pattern: 103 before: 363 now: 362 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 1537, fault_cnt:1527 +coverage: 95.133% pattern: 103 before: 362 now: 362 +checking valid circuit ... result: 1. diff --git a/exp_result/ATPG-LS_c880.bench.txt b/exp_result/ATPG-LS_c880.bench.txt new file mode 100644 index 0000000..1dae541 --- /dev/null +++ b/exp_result/ATPG-LS_c880.bench.txt @@ -0,0 +1,2708 @@ +make: 'atpg' is up to date. +======================== +parsing file ./benchmark/c880.bench ... Done. +====== Circuit Statistics ====== +PI: 60 +PO: 26 +Gate: 443 +Stem: 165 +Level: 6 +================================ +[SOL] flip: 0, stem: 0, fault:5605. flip_cnt: 0, stem_cnt: 165, fault_cnt:295 +coverage: 33.296% pattern: 1 before: 886 now: 591 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:3325. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 53.047% pattern: 2 before: 591 now: 416 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:1520. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 62.077% pattern: 3 before: 416 now: 336 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:2014. flip_cnt: 0, stem_cnt: 165, fault_cnt:298 +coverage: 74.041% pattern: 4 before: 336 now: 230 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 76.524% pattern: 5 before: 230 now: 208 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:565. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 81.151% pattern: 6 before: 208 now: 167 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 82.167% pattern: 7 before: 167 now: 158 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:418. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 84.650% pattern: 8 before: 158 now: 136 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 86.117% pattern: 9 before: 136 now: 123 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:152. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 87.020% pattern: 10 before: 123 now: 115 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 87.133% pattern: 11 before: 115 now: 114 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 87.923% pattern: 12 before: 114 now: 107 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 88.939% pattern: 13 before: 107 now: 98 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:266. flip_cnt: 0, stem_cnt: 165, fault_cnt:259 +coverage: 90.519% pattern: 14 before: 98 now: 84 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:247. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 91.986% pattern: 15 before: 84 now: 71 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 92.551% pattern: 16 before: 71 now: 66 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 92.664% pattern: 17 before: 66 now: 65 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 93.002% pattern: 18 before: 65 now: 62 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:187 +coverage: 93.002% pattern: 18 before: 62 now: 62 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:171. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 94.018% pattern: 19 before: 62 now: 53 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:286 +coverage: 94.244% pattern: 20 before: 53 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194 +coverage: 94.244% pattern: 20 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:187 +coverage: 94.244% pattern: 20 before: 51 now: 51 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 165, fault_cnt:336 +coverage: 94.695% pattern: 21 before: 51 now: 47 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:76. flip_cnt: 0, stem_cnt: 165, fault_cnt:291 +coverage: 95.147% pattern: 22 before: 47 now: 43 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:57. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 95.485% pattern: 23 before: 43 now: 40 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:192 +coverage: 95.711% pattern: 24 before: 40 now: 38 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:284 +coverage: 95.937% pattern: 25 before: 38 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271 +coverage: 95.937% pattern: 25 before: 36 now: 36 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 96.050% pattern: 26 before: 36 now: 35 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 96.275% pattern: 27 before: 35 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 96.275% pattern: 27 before: 33 now: 33 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:95. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 96.840% pattern: 28 before: 33 now: 28 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 96.953% pattern: 29 before: 28 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 96.953% pattern: 29 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 96.953% pattern: 29 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 96.953% pattern: 29 before: 27 now: 27 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 97.178% pattern: 30 before: 27 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191 +coverage: 97.178% pattern: 30 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 97.178% pattern: 30 before: 25 now: 25 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:133. flip_cnt: 0, stem_cnt: 165, fault_cnt:333 +coverage: 97.968% pattern: 31 before: 25 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 97.968% pattern: 31 before: 18 now: 18 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 98.194% pattern: 32 before: 18 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195 +coverage: 98.194% pattern: 32 before: 16 now: 16 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 98.307% pattern: 33 before: 16 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 98.307% pattern: 33 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 98.307% pattern: 33 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 98.307% pattern: 33 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 98.307% pattern: 33 before: 15 now: 15 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 98.420% pattern: 34 before: 15 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:159 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 98.420% pattern: 34 before: 14 now: 14 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:268 +coverage: 98.533% pattern: 35 before: 14 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 98.533% pattern: 35 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 98.533% pattern: 35 before: 13 now: 13 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 98.646% pattern: 36 before: 13 now: 12 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:303 +coverage: 98.758% pattern: 37 before: 12 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 98.758% pattern: 37 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 98.758% pattern: 37 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 98.758% pattern: 37 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 98.758% pattern: 37 before: 11 now: 11 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 98.871% pattern: 38 before: 11 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:298 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:299 +coverage: 98.871% pattern: 38 before: 10 now: 10 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:308 +coverage: 98.984% pattern: 39 before: 10 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 98.984% pattern: 39 before: 9 now: 9 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:21. flip_cnt: 0, stem_cnt: 165, fault_cnt:182 +coverage: 99.210% pattern: 40 before: 9 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:313 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198 +coverage: 99.210% pattern: 40 before: 7 now: 7 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:308 +coverage: 99.436% pattern: 41 before: 7 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:316 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.436% pattern: 41 before: 5 now: 5 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:38. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.661% pattern: 42 before: 5 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:190 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:291 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283 +coverage: 99.661% pattern: 42 before: 3 now: 3 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:13. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.774% pattern: 43 before: 3 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:317 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:297 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:302 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:315 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:186 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:169 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:159 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:296 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:349 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:311 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:173 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:172 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.774% pattern: 43 before: 2 now: 2 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 99.887% pattern: 44 before: 2 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:315 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:178 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:284 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:306 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:164 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:265 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:177 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:200 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:297 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:271 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:186 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:323 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:176 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:173 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:166 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:171 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:185 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:166 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:283 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:257 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:300 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:287 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:308 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:179 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:248 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:254 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:286 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:184 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:174 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:161 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:206 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:266 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:189 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:272 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:197 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:204 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:183 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:289 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:198 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:275 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:217 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:176 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:219 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:238 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:314 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:259 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:301 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:277 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:194 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:188 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:170 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:261 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:205 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:318 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:255 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:247 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:270 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:299 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:202 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:268 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:282 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:252 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:211 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:280 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:232 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:175 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:190 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:274 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:167 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:209 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:224 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:267 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:196 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:180 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:241 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:203 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:262 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:208 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:249 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:335 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:223 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:195 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:279 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:193 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:191 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:169 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:264 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:231 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:273 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:263 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:210 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:230 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:237 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:212 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:192 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:242 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:227 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:294 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:222 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:300 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:239 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:312 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:178 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:226 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:228 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:240 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:253 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:243 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:292 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:229 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:165 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:207 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:251 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:218 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:269 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:303 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:250 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:199 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:201 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:276 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:260 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:245 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:278 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:213 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:163 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:281 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:225 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:215 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:258 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:234 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:246 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:216 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:214 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:298 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:221 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:220 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:244 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:236 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:0. flip_cnt: 0, stem_cnt: 165, fault_cnt:233 +coverage: 99.887% pattern: 44 before: 1 now: 1 +checking valid circuit ... result: 1. +[SOL] flip: 0, stem: 0, fault:19. flip_cnt: 0, stem_cnt: 165, fault_cnt:235 +coverage: 100.000% pattern: 45 before: 1 now: 0 +checking valid circuit ... result: 1. + +real 7m21.840s +user 7m21.806s +sys 0m0.012s